Skyworks Solutions Inc. SI5338B-B05723-GMR

Overview

SI5338B-B05723-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B05723-GMR datasheet, SI5338B-B05723-GMR pinout, SI5338B-B05723-GMR application, or SI5338B-B05723-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338B-B05723-GMR implements a two-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) followed by four independent MultiSynth™ synthesis blocks, each capable of integer or fractional frequency generation. Its core uses a low-noise VCO with Fvco ranging up to ~3.5 GHz, enabling simultaneous outputs at frequencies including 710 MHz (LVPECL/LVDS), 250 MHz (HCSL), and 350 MHz (SSTL/HSTL).

Each output driver supports format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent supply voltage (VDDOx = 1.4–3.63 V), and fine-grained control including ±45 ns programmable phase offset (<20 ps step), 1 ppm frequency increment/decrement, and configurable spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread).

Key Specifications

Pinout & Package

SI5338B-B05723-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B05723-GM and LMK04832RHAR, SI5338B-B05723-GMR delivers superior PCIe Gen 4 jitter performance (0.15–0.45 ps RMS vs. ≥0.65 ps), lower power (45 mA vs. 75 mA), and finer frequency resolution (1 ppb vs. 10 ppb), making it optimal for high-density, low-power, multi-standard timing in networking and compute platforms.

Availability

SI5338B-B05723-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video synchronization, and FPGA processor clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338B-B05723-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-standard serial interfaces - specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing where low jitter, flexible output formats, and compact footprint are critical.

FAQ

What is the maximum output frequency supported by SI5338B-B05723-GMR in LVPECL mode?

The SI5338B-B05723-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 12G-SDI applications without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), per the synthesis architecture constraints specified for the SI5338B-B05723-GMR.

Does SI5338B-B05723-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338B-B05723-GMR is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Its measured RMS jitter is 0.11–0.32 ps in SRNS mode (PLL BW 2–5 MHz, CDR = 10 MHz), satisfying the ≤0.32 ps requirement per PCI-SIG Base Spec 4.0. The SI5338B-B05723-GMR achieves this using its patented MultiSynth™ architecture with optimized loop bandwidth and low-noise VCO design.

Can SI5338B-B05723-GMR generate different output voltages on each channel?

Yes, SI5338B-B05723-GMR provides independent output buffer supplies (VDDO0–VDDO3), allowing each of its four output banks to be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices - for example, driving 1.8 V LVDS SerDes, 2.5 V SSTL memory controllers, and 3.3 V legacy peripherals from a single SI5338B-B05723-GMR without external level shifters.

What is the minimum input reference frequency accepted by SI5338B-B05723-GMR?

The SI5338B-B05723-GMR accepts input reference frequencies as low as 5 MHz on differential inputs (IN1/IN2, IN5/IN6) and single-ended inputs (IN3/IN4). In PLL bypass (clock buffer) mode, operation down to 1 MHz is supported, though loss-of-signal detection is disabled below 5 MHz. The device also supports external crystals from 8 to 30 MHz, with on-chip load capacitance tuning for 11–13 pF crystals.

How is SI5338B-B05723-GMR programmed, and is ClockBuilder Pro required?

SI5338B-B05723-GMR is programmed via its I²C/SMBus interface (SCL/SDA pins) using standard 7-bit addressing. While ClockBuilder Pro is the official Skyworks GUI tool for configuration and .cmb file generation, the SI5338B-B05723-GMR can also be programmed directly via custom firmware using documented register maps (Section 6 of Rev. 1.6 datasheet). All configuration - including output format, frequency, voltage, and spread spectrum - is stored in one-time-programmable (OTP) NVM.