Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B06143-GM

Name: SI5338B-B06143-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B06143-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338B-B06143-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B06143-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,413

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338B-B06143-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B06143-GM datasheet, SI5338B-B06143-GM pinout, SI5338B-B06143-GM application, or SI5338B-B06143-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5–3.3 V), programmable phase/frequency increment (±45 ns / 20 ps step), spread-spectrum capability (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338B-B06143-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving one output pair. Each MultiSynth supports integer or fractional mode with <1 ppb frequency resolution and enables true zero-ppm accuracy on all outputs.

It features flexible input support - including 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential inputs - and fully independent output configuration per driver for signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5/1.8/2.5/3.3 V), and slew rate. The device operates across –40 to +85 °C with 45 mA typical core current.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently selectable
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail
Temperature Range	–40 to +85 °C ambient; qualified for industrial and telecom line card deployment
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management

Pinout & Package

SI5338B-B06143-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B	Differential output 0	Configurable as LVPECL/LVDS/HCSL/CML; independent VDDO0 supply (1.5–3.3 V)
CLK1A, CLK1B	Differential output 1	Same format and voltage flexibility as CLK0; fully independent frequency/phase control
CLK2A, CLK2B	Differential output 2	Supports same formats; enables multi-protocol clocking (e.g., PCIe + Ethernet + FPGA)
CLK3A, CLK3B	Differential output 3	Final independent output; usable for redundant clock or secondary domain timing
SCL, SDA	I²C/SMBus interface	Standard 2-wire serial programming; supports 400 kHz fast-mode operation
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events
VDD, VDDO0–VDDO3	Power supplies	Separate core (VDD) and per-output buffer (VDDOx) rails enable mixed-voltage system integration
GND, RSVD_GND	Ground connections	Multiple GND pins and reserved ground pad ensure low-noise return paths and thermal dissipation

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Four independent fractional-N synthesizers enabling simultaneous any-frequency generation (0.16–710 MHz) with 0 ppm precision per output
PCIe Gen 1–4 compliance	Validated for PCIe Gen 3 SRNS and Gen 4 common clock jitter specs (≤0.32 ps RMS and ≤0.45 ps RMS respectively)
Independent output voltage control	Each of four VDDO rails (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V, enabling direct interfacing with mixed-voltage SoCs/FPGAs
Programmable phase/frequency adjustment	Glitchless real-time tuning via PINC/FDEC pins: ±45 ns range, 20 ps step resolution, 667 ns update time (>18 MHz outputs)
Spread spectrum clocking (SSC)	Per-output SSC with user-selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and center/down-spread mode
Loss-of-lock and loss-of-signal detection	Dedicated INTR pin asserts on LOL (5–10 ms detect time) or LOS (2.6–5 µs detect time), enabling system-level fault monitoring

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center top-of-rack (ToR) switch. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and SSC support. Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 common clock compliance (≤0.45 ps RMS jitter) and reduces board area by >60% versus discrete solution.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in carrier-grade Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output formatting (LVDS for PHYs, HCSL for SerDes, CMOS for control logic). Use Value: Enables single-device timing for heterogeneous Ethernet subsystems; supports IEEE 802.3bj/802.3by jitter requirements via sub-1 ps RMS performance.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 297 MHz, ST 2081 (6G-SDI) 148.5 MHz, and auxiliary sync clocks in broadcast video equipment. IC Role / Device Role / Timing Role: High-precision quad clock generator with ultra-low jitter (<1 ps RMS) and deterministic phase alignment across outputs. Use Value: Meets SMPTE ST 2082 jitter mask (≤0.3 UI pk-pk) at 297 MHz; eliminates timing-induced pixel errors and frame sync failures.	Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in radar processing and AI inference accelerators. IC Role / Device Role / Timing Role: Configurable clock source supporting DDR4/DDR5 memory interfaces (SSTL-18/12), transceivers (HCSL/LVDS), and logic domains (CMOS). Use Value: Reduces BOM count by consolidating multiple clock sources; enables dynamic frequency scaling via I²C or hardware pin control.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center top-of-rack (ToR) switch.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and SSC support.

Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 common clock compliance (≤0.45 ps RMS jitter) and reduces board area by >60% versus discrete solution.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in carrier-grade Ethernet switches.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output formatting (LVDS for PHYs, HCSL for SerDes, CMOS for control logic).

Use Value: Enables single-device timing for heterogeneous Ethernet subsystems; supports IEEE 802.3bj/802.3by jitter requirements via sub-1 ps RMS performance.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 297 MHz, ST 2081 (6G-SDI) 148.5 MHz, and auxiliary sync clocks in broadcast video equipment.

IC Role / Device Role / Timing Role: High-precision quad clock generator with ultra-low jitter (<1 ps RMS) and deterministic phase alignment across outputs.

Use Value: Meets SMPTE ST 2082 jitter mask (≤0.3 UI pk-pk) at 297 MHz; eliminates timing-induced pixel errors and frame sync failures.

Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in radar processing and AI inference accelerators.

IC Role / Device Role / Timing Role: Configurable clock source supporting DDR4/DDR5 memory interfaces (SSTL-18/12), transceivers (HCSL/LVDS), and logic domains (CMOS).

Use Value: Reduces BOM count by consolidating multiple clock sources; enables dynamic frequency scaling via I²C or hardware pin control.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06143-GM	Same silicon, different factory-programmed NVM configuration; lacks pre-loaded PCIe Gen 4 SRNS profile	Requires full ClockBuilder Pro reconfiguration for PCIe Gen 4 compliance; no out-of-box SRNS support	Select SI5338B-B06143-GM when PCIe Gen 4 SRNS timing is required without custom programming.
ICS85411AGI-01LFT	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 0.1–700 MHz range	Limited to pre-defined frequencies; no spread spectrum, phase adjustment, or multi-format outputs	Choose ICS85411AGI-01LFT only for cost-sensitive, static-clock applications where programmability is unnecessary.

Compared with Si5338A-B06143-GM and ICS85411AGI-01LFT, the SI5338B-B06143-GM delivers unique value through factory-validated PCIe Gen 4 SRNS timing, real-time hardware-based frequency/phase tuning, and per-output voltage/format flexibility - reducing design validation effort and enabling field-upgradable timing configurations.

Availability

SI5338B-B06143-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338B-B06143-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.

The SI5338B-B06143-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-speed serial interface timing in datacenter, telecom, and broadcast systems requiring low jitter, multi-protocol flexibility, and field-reprogrammability.

FAQ

What is the primary function of the SI5338B-B06143-GM?

The SI5338B-B06143-GM is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. It replaces multiple discrete oscillators in applications like PCIe Gen 4 switches and Ethernet routers. Its MultiSynth™ technology enables any-frequency generation (0.16–710 MHz) with 0 ppm accuracy per output, and it is factory-configured for PCIe Gen 3 SRNS and Gen 4 common clock compliance.

Does the SI5338B-B06143-GM support spread spectrum clocking (SSC)?

Yes, the SI5338B-B06143-GM supports per-output spread spectrum clocking with user-selectable parameters: spread magnitude (0.5–5.0%), modulation rate (33–63 kHz), and center/down-spread mode. This feature is implemented in hardware and can be enabled independently on any output via I²C register configuration or ClockBuilder Pro software. The SI5338B-B06143-GM's SSC capability helps reduce EMI in dense PCB layouts without compromising timing integrity.

What input reference options does the SI5338B-B06143-GM support?

The SI5338B-B06143-GM supports four input reference types: (1) 8–30 MHz crystal oscillator (differential, internal load capacitance), (2) 5–200 MHz CMOS-level single-ended clock on IN3/IN4, (3) 5–350 MHz SSTL/HSTL on IN3/IN4, and (4) 5–710 MHz differential clock on IN1/IN2 or IN5/IN6. All inputs include loss-of-signal detection, and the device automatically selects the active reference based on configuration and signal presence.

How is phase alignment controlled across the four outputs of the SI5338B-B06143-GM?

The SI5338B-B06143-GM provides independent programmable phase offset on each output with <20 ps step resolution and ±45 ns total range. Phase alignment is achieved via dedicated registers controlling the MultiSynth™ divider phase accumulator. For integer-related frequencies, output-to-output skew is guaranteed ≤100 ps. The device also supports initial phase offset programming during startup, enabling deterministic inter-output timing relationships critical for SerDes and memory interface applications.

Is ClockBuilder Pro software required to configure the SI5338B-B06143-GM?

No, ClockBuilder Pro is optional but strongly recommended for efficient configuration of the SI5338B-B06143-GM. The device supports full I²C/SMBus register-level programming, allowing custom firmware to write configuration values directly. However, ClockBuilder Pro automates complex tasks - including jitter optimization, PCIe compliance validation, SSC setup, and pin-compatible configuration export - and is required to generate the factory-programmed NVM image used in the SI5338B-B06143-GM variant.

SI5338B-B06143-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B06143-GM FAQ

1.How can I place an order for SI5338B-B06143-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B06143-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B06143-GM reliable?

The price and inventory of SI5338B-B06143-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B06143-GM is usually 5 days.

3.What payment methods are accepted for SI5338B-B06143-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B06143-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B06143-GM?

SI5338B-B06143-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B06143-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B06143-GM?

For technical support, including SI5338B-B06143-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B06143-GM requirements.

6.How does Aetrix verify that SI5338B-B06143-GM is sourced from the original manufacturer or authorized distributors?

All SI5338B-B06143-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B06143-GM meets industry standards.

7.What is the process for return or replacement of SI5338B-B06143-GM?

All SI5338B-B06143-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B06143-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B06143-GM part is unused and in its original packaging.

Return procedure for SI5338B-B06143-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…