Skyworks Solutions Inc. SI5338B-B06143-GMR
- Part No.:
- SI5338B-B06143-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338B-B06143-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338B-B06143-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338B-B06143-GMR datasheet, SI5338B-B06143-GMR pinout, SI5338B-B06143-GMR application, or SI5338B-B06143-GMR equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step accuracy, spread-spectrum capability (0.5–5.0% deviation), and external crystal input support (8–30 MHz).
Technical Context
The SI5338B-B06143-GMR implements a two-stage PLL architecture: a high-stability reference stage feeding a fractional-N MultiSynth™ synthesis stage per output, enabling independent integer/fractional frequency generation with <1 ppb resolution. Each output driver supports format- and voltage-selectable termination with programmable slew rate control.
It integrates loss-of-lock and loss-of-signal detection, independent output enable (OEB), phase/frequency increment/decrement via dedicated pins or I²C, and zero-delay mode via external feedback. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and output buffer supplies from 1.4 V to 3.63 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output |
| Output Frequency Range | 0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz) |
| Synthesis Resolution | 1 ppb - enables true zero-ppm frequency accuracy on all four outputs simultaneously |
| Input Reference Options | 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - provides flexible clock source integration |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V - allows mixed-voltage system interfacing without level shifters |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments |
Pinout & Package
The SI5338B-B06143-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS-level inputs; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential output pairs | Four independent output drivers; each configurable as LVPECL, LVDS, HCSL, CML, or SSTL/HSTL |
| VDDO0–VDDO3 | Output buffer supply rails | Independent 1.5/1.8/2.5/3.3 V supplies per output bank - enables mixed-signal interface |
| VDD | Core supply | 1.8 V / 2.5 V / 3.3 V core power; PSRR optimized for low-noise timing operation |
| SCL, SDA | I²C interface | SMBus-compatible serial bus (up to 400 kHz) for configuration and status monitoring |
| INTR | Interrupt output | Open-drain alarm signal indicating loss-of-lock or loss-of-signal events |
| OEB, PINC, FINC | Control inputs | Hardware-controlled output enable and glitchless frequency/phase adjustment (1 ppm / 20 ps steps) |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables independent any-frequency generation on all four outputs with zero ppm error and <1 ppb resolution |
| PCIe Gen 1–4 compliance | Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS), validated with Intel Clock Jitter Tool |
| Flexible output configuration | Each output supports selectable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and drive strength |
| Spread-spectrum clocking | Configurable on any output: 5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation rate - reduces EMI in dense systems |
| Glitchless frequency tuning | Hardware pin-controlled frequency increment/decrement in 1 ppm steps with <667 ns update time above 18 MHz |
| Programmable phase offset | ±45 ns initial phase adjustment per output with <20 ps step resolution - enables precise skew management |
Applications
| Processor and FPGA Clocking | PCIe Gen 1–4 Timing |
|---|---|
Use Scenario: Providing multiple synchronized clocks to heterogeneous SoCs, FPGAs, and ASICs in high-performance computing or AI accelerator boards. IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent, low-jitter clocks for core logic, memory interfaces, and SerDes lanes. Use Value: Eliminates need for four discrete oscillators; enables dynamic frequency scaling and phase alignment across domains using I²C or hardware pins. | Use Scenario: Generating compliant reference clocks for PCIe root complexes and endpoints in servers, storage controllers, and NICs. IC Role / Device Role / Timing Role: PCIe Common Clock generator meeting Gen 3 SRNS and Gen 4 jitter requirements (0.11–0.45 ps RMS). Use Value: Validates against Intel Clock Jitter Tool; supports both common clock and separate reference architectures without redesign. |
| Ethernet Switch/Routing | Broadcast Video/Audio Timing |
Use Scenario: Supplying synchronous clocks to multi-port 1/10 GbE PHYs, packet processors, and TCAMs in enterprise switches and routers. IC Role / Device Role / Timing Role: Low-jitter (0.7 ps RMS) clock source for IEEE 802.3-compliant PHYs and PTP timestamping circuits. Use Value: Meets GbE random jitter spec (0.38 ps RMS, 1.875–20 MHz); supports dual-rate 1G/10G clocking from one device. | Use Scenario: Delivering frame-synchronized clocks to SDI transceivers, video encoders, and audio DSPs in broadcast infrastructure equipment. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks. Use Value: Achieves sub-10 ps cycle-cycle jitter; supports simultaneous generation of multiple video/audio rates with deterministic phase relationships. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B06143-GMR | Same pinout and register map; differs only in factory-programmed NVM configuration - B06143 variant preloaded with specific frequency plan | Identical use cases; no functional difference in field programming or runtime behavior | Select B06143-GMR variants when preconfigured startup frequencies are required; A/B/C suffix denotes NVM content, not silicon revision |
| LMK04832RHAR | Two PLLs (not four independent MultiSynths); higher power (125 mA vs. 45 mA typ); larger 48-QFN package; supports JESD204B deterministic latency | Better suited for JESD204B baseband applications; less optimal for PCIe Gen 4 or multi-protocol clock translation | Choose LMK04832RHAR only when deterministic latency or dual-loop redundancy is mandatory; SI5338B-B06143-GMR offers superior jitter and density for general-purpose quad clocking |
Compared with Si5338A-B06143-GMR, the SI5338B-B06143-GMR shares identical silicon and pinout but ships with a different factory-loaded configuration image; versus LMK04832RHAR, it delivers lower jitter (0.7 vs. 0.9 ps RMS), 45% lower core current, and 44% smaller footprint - critical for space-constrained PCIe and networking designs.
Availability
SI5338B-B06143-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, and processor/FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for SI5338B-B06143-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed for high-precision, multi-output clock generation in datacenter, telecom, and broadcast systems where low jitter, flexible frequency synthesis, and compact packaging are essential.
FAQ
What is the primary function of the SI5338B-B06143-GMR?
The SI5338B-B06143-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. Its MultiSynth™ architecture enables any-frequency generation (0.16–710 MHz) with 0 ppm precision, making it ideal for replacing multiple crystal oscillators in networking and computing systems. The SI5338B-B06143-GMR supports PCIe Gen 1–4, Ethernet, and broadcast video timing standards.
Does the SI5338B-B06143-GMR support spread-spectrum clocking (SSC)?
Yes, the SI5338B-B06143-GMR supports highly configurable spread-spectrum clocking on any output: frequency range 5–350 MHz, spread magnitude 0.5–5.0%, and modulation rate 33–63 kHz. This feature is implemented digitally within the MultiSynth™ engine and requires no external components. The SI5338B-B06143-GMR's SSC capability helps reduce electromagnetic interference in dense PCB layouts without compromising timing integrity.
What input reference sources does the SI5338B-B06143-GMR accept?
The SI5338B-B06143-GMR accepts four types of input references: (1) 8–30 MHz fundamental-mode crystals connected to IN1/IN2, (2) 5–200 MHz CMOS-level signals on IN3/IN4, (3) 5–350 MHz SSTL/HSTL inputs, and (4) 5–710 MHz differential AC-coupled clocks on IN1/IN2 or IN5/IN6. All inputs support automatic loss-of-signal detection with 2.6–5 µs response time. The SI5338B-B06143-GMR does not require external buffering for most crystal configurations.
How is output voltage configured on the SI5338B-B06143-GMR?
Each of the four output banks (CLK0–CLK3) has its own dedicated VDDOx supply pin (VDDO0–VDDO3), allowing independent selection of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per bank. This eliminates level-shifting components when driving mixed-voltage devices such as 1.8 V FPGAs and 3.3 V PHYs from a single SI5338B-B06143-GMR. The SI5338B-B06143-GMR's output drivers auto-detect VDDOx voltage and configure drive strength accordingly.
Can the SI5338B-B06143-GMR generate frequencies above 350 MHz?
Yes, the SI5338B-B06143-GMR supports output frequencies up to 710 MHz in LVPECL/LVDS modes, but only two unique frequencies above 350 MHz may be active simultaneously - specifically Fvco/4 and Fvco/6 - due to internal VCO constraints. Frequencies between 350–473.33 MHz and 550–710 MHz are supported, while 473.33–550 MHz is a gap region. The SI5338B-B06143-GMR's datasheet specifies this limitation explicitly in Table 6 footnote 6.
SI5338B-B06143-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338B-B06143-GMR FAQ
1.How can I place an order for SI5338B-B06143-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338B-B06143-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338B-B06143-GMR reliable?
The price and inventory of SI5338B-B06143-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B06143-GMR is usually 5 days.
3.What payment methods are accepted for SI5338B-B06143-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B06143-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338B-B06143-GMR?
SI5338B-B06143-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338B-B06143-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338B-B06143-GMR?
For technical support, including SI5338B-B06143-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B06143-GMR requirements.
6.How does Aetrix verify that SI5338B-B06143-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338B-B06143-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B06143-GMR meets industry standards.
7.What is the process for return or replacement of SI5338B-B06143-GMR?
All SI5338B-B06143-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B06143-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338B-B06143-GMR part is unused and in its original packaging.
Return procedure for SI5338B-B06143-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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