Skyworks Solutions Inc. SI5338B-B06189-GMR

Overview

SI5338B-B06189-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338B-B06189-GMR datasheet, SI5338B-B06189-GMR pinout, SI5338B-B06189-GMR application, or SI5338B-B06189-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage control (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz.

Technical Context

The SI5338B-B06189-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output path includes programmable R-divider, M-divider, and P-divider stages enabling any-frequency synthesis from 0.16 MHz to 710 MHz with true zero-ppm accuracy when operating in integer mode.

It supports flexible reference inputs - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and glitchless frequency increment/decrement via dedicated pins or I²C.

Key Specifications

Pinout & Package

SI5338B-B06189-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06189-GM, SI5338B-B06189-GMR offers broader legacy interface support and field-proven PCIe Gen 4 compatibility, while ICS8430I-01T provides lower BOM cost and faster time-to-market for static clock trees - making SI5338B-B06189-GMR optimal for programmable, multi-standard industrial and telecom timing.

Availability

SI5338B-B06189-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10 GbE switch fabrics, and FPGA-based broadcast video synchronizers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338B-B06189-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, networking, and broadcast equipment - emphasizing low jitter, multi-format output flexibility, and robust industrial temperature operation.

FAQ

What is the primary function of the SI5338B-B06189-GMR?

The SI5338B-B06189-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. It replaces up to four discrete oscillators in systems requiring precise, configurable timing - such as PCIe Gen 4 root complexes, Ethernet switches, and FPGA-based video synchronizers. Its MultiSynth™ architecture ensures 0 ppm frequency accuracy in integer mode and supports LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL output formats.

Does the SI5338B-B06189-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338B-B06189-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' validated settings. It is explicitly listed in the datasheet as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant. Validation includes use of the Skyworks PCIe Clock Jitter Tool and adherence to Intel's jitter filter profile for Gen 4 compliance testing.

Can the SI5338B-B06189-GMR generate different output voltages simultaneously?

Yes, the SI5338B-B06189-GMR supports independent output buffer supply voltages (VDDO0–VDDO3) per driver, allowing simultaneous 1.5 V, 1.8 V, 2.5 V, and 3.3 V outputs. This enables direct interfacing with mixed-voltage components - for example, driving a 1.8 V FPGA transceiver bank and a 3.3 V Ethernet PHY from the same device without level shifters.

How is the SI5338B-B06189-GMR programmed and configured?

The SI5338B-B06189-GMR is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. This GUI tool generates custom configuration files, validates timing constraints, and exports register maps for production programming. Configuration can be stored in on-chip OTP memory for autonomous startup, or loaded dynamically during system initialization.

What package type and pin count does the SI5338B-B06189-GMR use?

The SI5338B-B06189-GMR uses a 4 × 4 mm, 24-pin QFN package with exposed thermal pad (GMR suffix). It has four differential output pairs (CLK0A/B through CLK3A/B), six clock inputs (IN1–IN6), four independent VDDO pins, core VDD, I²C (SCL/SDA), interrupt (INTR), and multiple GND connections - matching the standard Si5338 pinout defined in Skyworks' datasheet Rev. 1.6.