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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B06190-GMR

Name: SI5338B-B06190-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B06190-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B06190-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B06190-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Inventory:3,980

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Product details

Overview

SI5338B-B06190-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338B-B06190-GMR datasheet, SI5338B-B06190-GMR pinout, SI5338B-B06190-GMR application, or SI5338B-B06190-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338B-B06190-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider for reference conditioning, followed by four independent MultiSynth™ fractional-N synthesis blocks (M0–M3) each feeding a dedicated output driver. Each synthesis block supports integer or fractional mode with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).

Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, independent VDDO supply per bank (VDDO0–VDDO3), and glitchless frequency increment/decrement via dedicated pins (FINC/FDEC) or I²C. Loss-of-lock and loss-of-signal monitoring are integrated with interrupt reporting on INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential outputs (CLK0A/B–CLK3A/B) or up to 8 single-ended; supports mixed-mode configuration
Frequency range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 Common Clock specs
Input reference support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply & temp	Core: 1.8/2.5/3.3 V ±10%; output buffers: 1.4–3.63 V; operating range: –40 to +85 °C
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338B-B06190-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL at 5–350 MHz; DC-coupled with internal biasing
CLK0A/CLK0B–CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with per-bank VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank enable mixed-voltage system interfacing
SCL/SDA	I²C programming interface	SMBus-compatible 100/400 kHz; supports in-system configuration and dynamic reprogramming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or NVM write completion

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously
Glitchless frequency tuning	Pin-controlled FINC/FDEC inputs allow real-time 1 ppm-step adjustments without output interruption
Per-output phase control	Programmable initial phase offset (±45 ns) and <20 ps step resolution for skew management
Spread-spectrum clocking	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI
Zero-delay mode	External feedback path enables synchronous buffering with minimal propagation delay (2.5–4 ns)

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to multiple PCIe Gen 4 endpoints and Ethernet PHYs on a high-density switch ASIC board. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 Common Clock and IEEE 802.3bj jitter masks. Use Value: Eliminates need for four discrete oscillators; reduces BOM count and layout area while maintaining <0.45 ps RMS jitter compliance.	Use Scenario: Generating 156.25 MHz SerDes reference, 250 MHz CPU clock, 125 MHz PHY interface, and 100 MHz management bus clock in a 10 GbE line card. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output formatting (LVDS, HCSL, CMOS) and voltage control (1.8 V, 2.5 V, 3.3 V). Use Value: Enables single-chip timing for heterogeneous subsystems; avoids level-shifting components and interposer routing complexity.
FPGA-Based Video Processing	Telecom Line Card Clock Translation
Use Scenario: Driving FPGA transceivers (GTY/GTP), DDR4 memory controller, video processing core, and HDMI PHY with precisely phased clocks in broadcast-grade video encoder. IC Role / Device Role / Timing Role: Programmable quad clock source supporting LVDS (156.25 MHz), HCSL (312.5 MHz), CMOS (100 MHz), and SSTL (200 MHz) outputs. Use Value: Achieves sub-20 ps inter-output skew and <0.7 ps RMS jitter required for 4K60 video frame integrity and HDMI 2.0 compliance.	Use Scenario: Translating OC-192 (9.953 Gbps) line rate to SONET/SDH framing clocks (155.52 MHz, 622.08 MHz) and backplane interfaces (100 MHz, 125 MHz) in a multi-service access node. IC Role / Device Role / Timing Role: Frequency translator with ultra-low additive jitter (<0.165 ps RMS in buffer mode) and dual-reference input flexibility. Use Value: Maintains BER <10⁻¹² over temperature; supports hitless switchover between primary and backup references via I²C reconfiguration.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to multiple PCIe Gen 4 endpoints and Ethernet PHYs on a high-density switch ASIC board.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 Common Clock and IEEE 802.3bj jitter masks.

Use Value: Eliminates need for four discrete oscillators; reduces BOM count and layout area while maintaining <0.45 ps RMS jitter compliance.

Use Scenario: Generating 156.25 MHz SerDes reference, 250 MHz CPU clock, 125 MHz PHY interface, and 100 MHz management bus clock in a 10 GbE line card.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output formatting (LVDS, HCSL, CMOS) and voltage control (1.8 V, 2.5 V, 3.3 V).

Use Value: Enables single-chip timing for heterogeneous subsystems; avoids level-shifting components and interposer routing complexity.

FPGA-Based Video Processing

Telecom Line Card Clock Translation

Use Scenario: Driving FPGA transceivers (GTY/GTP), DDR4 memory controller, video processing core, and HDMI PHY with precisely phased clocks in broadcast-grade video encoder.

IC Role / Device Role / Timing Role: Programmable quad clock source supporting LVDS (156.25 MHz), HCSL (312.5 MHz), CMOS (100 MHz), and SSTL (200 MHz) outputs.

Use Value: Achieves sub-20 ps inter-output skew and <0.7 ps RMS jitter required for 4K60 video frame integrity and HDMI 2.0 compliance.

Use Scenario: Translating OC-192 (9.953 Gbps) line rate to SONET/SDH framing clocks (155.52 MHz, 622.08 MHz) and backplane interfaces (100 MHz, 125 MHz) in a multi-service access node.

IC Role / Device Role / Timing Role: Frequency translator with ultra-low additive jitter (<0.165 ps RMS in buffer mode) and dual-reference input flexibility.

Use Value: Maintains BER <10⁻¹² over temperature; supports hitless switchover between primary and backup references via I²C reconfiguration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06190-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant)	Identical functional scope; B-variant includes pre-loaded PCIe Gen 4 timing profile	Select SI5338B-B06190-GMR when PCIe Gen 4 Common Clock compliance and factory-tuned jitter performance are required out-of-box.
LMK04832ISQE/NOPB	Two PLLs (not four independent synthesizers); higher power (120 mA typ); larger 48-QFN package	Better suited for ultra-low-noise RF sampling clocks; less flexible for multi-protocol, multi-voltage systems	Choose LMK04832ISQE/NOPB only if sub-0.1 ps RMS jitter below 100 kHz offset is mandatory and board area allows 48-pin footprint.

Compared with Si5338A-B06190-GMR, the SI5338B-B06190-GMR delivers identical hardware functionality but ships with PCIe Gen 4-optimized firmware; versus LMK04832ISQE/NOPB, it offers superior integration density, lower power, and finer-grained per-output configurability at the expense of absolute lowest-phase-noise performance.

Availability

SI5338B-B06190-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE telecom switches, and FPGA-based broadcast video equipment requiring stable component supply and long-term production continuity.

Supply support for SI5338B-B06190-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single programmable clock generator for high-speed serial interfaces including PCIe, Ethernet, and Fibre Channel, emphasizing low jitter, flexible output formatting, and field-reprogrammability.

FAQ

What is the factory-programmed configuration of SI5338B-B06190-GMR?

The SI5338B-B06190-GMR ships with non-volatile memory (NVM) pre-programmed for PCIe Gen 4 Common Clock operation: 100 MHz LVDS outputs on CLK0A/B and CLK1A/B, 125 MHz HCSL on CLK2A/B, and 100 MHz CMOS on CLK3A/B, all meeting PCIe Gen 4 jitter requirements. This eliminates initial configuration effort for standard use cases.

Does SI5338B-B06190-GMR support spread-spectrum clocking on all outputs?

Yes, SI5338B-B06190-GMR supports independent spread-spectrum clocking (SSC) on any output, with programmable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). SSC is enabled per-output via register settings and does not require external components.

Can SI5338B-B06190-GMR generate frequencies above 350 MHz on multiple outputs simultaneously?

Yes, but with constraint: SI5338B-B06190-GMR can output two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-due to VCO architecture limits. All other outputs must be ≤350 MHz or integer-related to those two high-frequency outputs.

What is the minimum input frequency supported in PLL bypass (buffer) mode for SI5338B-B06190-GMR?

In PLL bypass mode, SI5338B-B06190-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is only functional above 5 MHz.

How is thermal performance managed in the 4 × 4 mm QFN package of SI5338B-B06190-GMR?

SI5338B-B06190-GMR uses a thermally enhanced 24-QFN package with exposed paddle. Its junction-to-ambient thermal resistance (θJA) is 37 °C/W under still air conditions, and junction-to-case (θJC) is 10 °C/W-enabling reliable operation at full load (60 mA core current) within the –40 to +85 °C range when mounted on a 2-layer PCB with adequate copper pour.

SI5338B-B06190-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B06190-GMR FAQ

1.How can I place an order for SI5338B-B06190-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B06190-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B06190-GMR reliable?

The price and inventory of SI5338B-B06190-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B06190-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B06190-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B06190-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B06190-GMR?

SI5338B-B06190-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B06190-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B06190-GMR?

For technical support, including SI5338B-B06190-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B06190-GMR requirements.

6.How does Aetrix verify that SI5338B-B06190-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B06190-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B06190-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B06190-GMR?

All SI5338B-B06190-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B06190-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B06190-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B06190-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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