Skyworks Solutions Inc. SI5338B-B08683-GMR

Overview

SI5338B-B08683-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering 0 ppm precision on all four outputs. It supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, operates from 1.8/2.5/3.3 V core supply, and achieves 0.7 ps RMS phase jitter (12 kHz–20 MHz). It is used in PCIe Gen 4 common-clock systems requiring low-jitter, multi-frequency timing.

For engineers reviewing the SI5338B-B08683-GMR datasheet, SI5338B-B08683-GMR pinout, SI5338B-B08683-GMR application, or SI5338B-B08683-GMR equivalent, key selection considerations include PCIe Gen 3/4 SRNS compliance, independent per-output voltage configuration (1.5–3.3 V), spread-spectrum control (0.5–5.0% at 33–63 kHz), and 24-pin 4×4 mm QFN package compatibility with high-density FPGA/ASIC clock trees.

Technical Context

The SI5338B-B08683-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or crystal (8–30 MHz) references.

Each output supports independent format selection, voltage rail assignment (VDDO0–VDDO3), phase offset (±45 ns in <20 ps steps), and frequency increment/decrement (1 ppm steps, glitchless). The device supports external feedback for zero-delay mode and provides loss-of-lock and loss-of-signal alarms via the INTR pin.

Key Specifications

Pinout & Package

SI5338B-B08683-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad (GND). Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). All power pins (VDD, VDDO0–VDDO3) are decoupled internally; external 0.1 µF ceramic capacitors required per VDDO rail.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D08683-GM and ICS8430I-01LG, SI5338B-B08683-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and 4-output density in a compact QFN-making it optimal for mid-tier FPGA/switch designs where reconfiguration and jitter margin are critical but 8-output complexity is unnecessary.

Availability

SI5338B-B08683-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video FPGA synchronization, and telecom line card sync requiring stable component supply and long-term lifecycle support.

Supply support for SI5338B-B08683-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family is designed for high-performance, multi-frequency clock generation in space-constrained systems-enabling replacement of multiple crystal oscillators with a single, software-configurable timing IC.

FAQ

What is the maximum output frequency supported by SI5338B-B08683-GMR in LVPECL mode?

The SI5338B-B08683-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This applies when using differential outputs with appropriate termination and layout practices. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), and jitter performance remains within specification at full range when using low-noise input references and proper power decoupling.

Does SI5338B-B08683-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338B-B08683-GMR is explicitly SRNS-compliant for PCIe Gen 3 and Gen 4. Its measured RMS jitter is ≤0.32 ps (Gen 3 SRNS) and ≤0.45 ps (Gen 4 common clock) under specified conditions (PLL BW 2–5 MHz, CDR = 10 MHz), meeting PCI-SIG Base Specification 4.0 requirements. Configuration requires setting appropriate PLL loop bandwidth and disabling spread spectrum.

Can SI5338B-B08683-GMR generate four different output frequencies simultaneously?

Yes, SI5338B-B08683-GMR can synthesize four independent frequencies simultaneously-one per output pair (CLK0, CLK1, CLK2, CLK3)-using its four dedicated MultiSynth™ engines. Each output supports any frequency from 0.16 MHz to 710 MHz with 0 ppm accuracy, and frequencies may be unrelated (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) without shared dividers or constraints.

What is the function of the INTR pin on SI5338B-B08683-GMR?

The INTR pin on SI5338B-B08683-GMR is an open-drain interrupt output that asserts low during loss-of-signal (LOS) or loss-of-lock (LOL) events. It is electrically compatible with 1.8/2.5/3.3 V logic and requires an external pull-up resistor. The pin enables real-time system monitoring and fault recovery without polling the I²C interface, improving system reliability in mission-critical timing applications.

Is ClockBuilder Pro software required to configure SI5338B-B08683-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338B-B08683-GMR configuration. While the device supports direct I²C register writes, ClockBuilder Pro provides GUI-based frequency planning, jitter analysis, pin assignment validation, and one-click .c file generation for embedded initialization. It eliminates manual register calculation errors and accelerates bring-up-especially for complex multi-output, multi-format configurations.