Skyworks Solutions Inc. SI5338B-B09440-GMR

Overview

SI5338B-B09440-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B09440-GMR datasheet, SI5338B-B09440-GMR pinout, SI5338B-B09440-GMR application, or SI5338B-B09440-GMR equivalent, key selection criteria include output format flexibility per channel, independent voltage supply per output bank (1.5–3.3 V), sub-1 ps RMS jitter performance at PCIe Gen 4, and I²C-based field reprogramming capability without hardware changes.

Technical Context

The SI5338B-B09440-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers. Each output driver is fully configurable for signal format, voltage, termination, and spread-spectrum modulation-enabling simultaneous generation of non-integer-related frequencies across differential and single-ended standards.

It supports six input sources (crystal, CMOS, SSTL/HSTL, differential), with loss-of-signal and loss-of-lock monitoring, programmable phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and output buffer supplies independently set per bank.

Key Specifications

Pinout & Package

The SI5338B-B09440-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D08589-GM and ICS8430I-01T, the SI5338B-B09440-GMR uniquely balances field programmability, multi-format flexibility, and PCIe Gen 4 compliance in a compact 24-QFN package-making it optimal for systems requiring post-deployment clock reconfiguration without layout revision.

Availability

SI5338B-B09440-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, broadcast video frame sync, and FPGA-based telecom line card applications requiring stable component supply and long-term production continuity.

Supply support for SI5338B-B09440-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple fixed-frequency oscillators with a single, software-configurable clock generator for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and telecom standards-while maintaining sub-picosecond jitter performance.

FAQ

What is the maximum output frequency supported by the SI5338B-B09440-GMR?

The SI5338B-B09440-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined in the synthesis architecture. All frequencies are synthesized with MultiSynth™ technology and zero ppm error.

Does the SI5338B-B09440-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338B-B09440-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) and is explicitly listed as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in its official documentation. Its 0.7 ps RMS typical phase jitter and programmable PLL bandwidth (1.6–4 MHz) ensure robust CDR lock under system-level noise conditions.

Can the SI5338B-B09440-GMR generate different output voltages on each channel?

Yes, the SI5338B-B09440-GMR provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows mixed-signal interfacing-for example, driving 1.8 V LVDS FPGA inputs and 3.3 V CMOS microcontrollers simultaneously-without external level shifters or multiple power domains.

How is the SI5338B-B09440-GMR programmed in-system?

The SI5338B-B09440-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) operating at up to 400 kHz. Configuration is performed using Skyworks' ClockBuilder Pro software, which generates register maps and supports real-time frequency/phase adjustments, spread-spectrum settings, and fault monitoring-all without requiring device reset or power cycle.

What package type and thermal characteristics does the SI5338B-B09440-GMR use?

The SI5338B-B09440-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C. The exposed pad must be soldered to a solid thermal plane per Skyworks' recommended land pattern.