Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B09791-GMR

Name: SI5338B-B09791-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B09791-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338B-B09791-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338B-B09791-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,452

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338B-B09791-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA/processor clocking, and broadcast video timing systems.

For engineers reviewing the SI5338B-B09791-GMR datasheet, SI5338B-B09791-GMR pinout, SI5338B-B09791-GMR application, or SI5338B-B09791-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe and Ethernet timing compliance, and real-world application context for high-speed serial interface clocking, frequency translation, and multi-voltage level translation.

Technical Context

The SI5338B-B09791-GMR integrates a fractional-N PLL with patented MultiSynth™ synthesis stages per output, enabling independent integer/fractional frequency generation from 0.16 MHz to 710 MHz. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable VDDO (1.5/1.8/2.5/3.3 V) and sub-20 ps phase step resolution.

It accepts flexible reference inputs: 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential. Loss-of-signal and loss-of-lock alarms, I²C/SMBus interface, and external feedback mode support zero-delay operation and system-level fault monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz HCSL, 155.52 MHz OC-12, and 125 MHz GbE clocks
Input Reference Support	8–30 MHz crystal or 5–710 MHz differential - enables direct replacement of multiple XO sources
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows mixed-voltage system clock distribution
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density FPGA/ASIC PCB layouts
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
PCIe Compliance	Gen 1/2/3/4 Common Clock & Gen 3 SRNS - validated per Intel Clock Jitter Tool v1.6.4

Pinout & Package

SI5338B-B09791-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family documentation and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended CMOS inputs	Support 5–200 MHz DC-coupled clocks; VIH/VIL referenced to VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for mixed-signal interface compatibility
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz control; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status flag for loss-of-signal or loss-of-lock events
VDD	Core supply	Single 1.8/2.5/3.3 V supply; 45 mA typical core current at 100 MHz on all outputs
GND, RSVD_GND	Ground terminals	Multiple ground pins including reserved ground for noise isolation and thermal dissipation

Key Features

Feature	Design Value
Independent MultiSynth™ per output	Enables true zero-ppm frequency accuracy on all four outputs simultaneously without shared dividers
Programmable phase offset	±45 ns adjustment in <20 ps steps - critical for skew alignment in multi-lane SerDes interfaces
Glitchless frequency tuning	1 ppm increment/decrement via pin or I²C - maintains continuous clock output during dynamic rate changes
Spread spectrum control	0.5–5.0% spread at 33–63 kHz modulation - reduces EMI in dense PCB layouts without affecting timing margin
Flexible reference input	Crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) - eliminates need for external buffers or level shifters

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent, low-jitter clocks to SERDES lanes, packet processors, and management controllers. Use Value: Eliminates four discrete oscillators while meeting IEEE 802.3 and PCIe jitter specs - reduces BOM count and layout complexity.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, requiring Common Clock architecture with <0.45 ps RMS jitter. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz HCSL clocks to root complex and endpoints with SRNS validation. Use Value: Meets PCIe Gen 4 Common Clock TJ spec (20.1–33.6 ps pk-pk) and Gen 3 SRNS requirement (<0.32 ps RMS) without external filtering.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: SMPTE 2110 IP media gateway needing precise 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with sub-10 ps skew. IC Role / Device Role / Timing Role: Multi-frequency synthesizer generating frame-synced clocks for encoder/decoder ASICs and transport interfaces. Use Value: Achieves <100 ps output-to-output skew and ±45 ns programmable phase offset - enables pixel-accurate genlock across video pipelines.	Use Scenario: Xilinx Versal or Intel Agilex FPGA-based edge AI accelerator requiring separate clocks for PL logic, DDR4 memory, and ARM cores. IC Role / Device Role / Timing Role: Configurable clock hub supplying LVDS (for DDR), HCSL (for PCIe), and CMOS (for peripherals) from one device. Use Value: Supports mixed-output formats and voltages (1.8 V DDR, 3.3 V GPIO) - avoids level translators and simplifies power domain partitioning.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent, low-jitter clocks to SERDES lanes, packet processors, and management controllers.

Use Value: Eliminates four discrete oscillators while meeting IEEE 802.3 and PCIe jitter specs - reduces BOM count and layout complexity.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, requiring Common Clock architecture with <0.45 ps RMS jitter.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz HCSL clocks to root complex and endpoints with SRNS validation.

Use Value: Meets PCIe Gen 4 Common Clock TJ spec (20.1–33.6 ps pk-pk) and Gen 3 SRNS requirement (<0.32 ps RMS) without external filtering.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: SMPTE 2110 IP media gateway needing precise 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with sub-10 ps skew.

IC Role / Device Role / Timing Role: Multi-frequency synthesizer generating frame-synced clocks for encoder/decoder ASICs and transport interfaces.

Use Value: Achieves <100 ps output-to-output skew and ±45 ns programmable phase offset - enables pixel-accurate genlock across video pipelines.

Use Scenario: Xilinx Versal or Intel Agilex FPGA-based edge AI accelerator requiring separate clocks for PL logic, DDR4 memory, and ARM cores.

IC Role / Device Role / Timing Role: Configurable clock hub supplying LVDS (for DDR), HCSL (for PCIe), and CMOS (for peripherals) from one device.

Use Value: Supports mixed-output formats and voltages (1.8 V DDR, 3.3 V GPIO) - avoids level translators and simplifies power domain partitioning.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B09791-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant)	Identical electrical performance; B-variant includes pre-loaded PCIe Gen 4 timing profile	Select SI5338B-B09791-GMR when PCIe Gen 4 Common Clock compliance is required out-of-box
LMK04832ISQE/NOPB	Two PLLs, eight outputs, higher power (120 mA); no integrated crystal drive; requires external VCXO	Targeted at ultra-low-jitter RF and instrumentation; lacks built-in crystal oscillator support	Choose LMK04832 for sub-0.1 ps RMS jitter needs or when dual-loop jitter cleaning is required

Compared with Si5338A-B09791-GMR, the SI5338B-B09791-GMR delivers identical hardware but ships with PCIe Gen 4-optimized firmware; versus LMK04832, it offers lower power, integrated crystal support, and simpler I²C programming at the cost of fewer outputs and higher integrated jitter floor.

Availability

SI5338B-B09791-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 server platforms, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for SI5338B-B09791-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single programmable clock generator for high-speed serial interfaces - targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing applications.

FAQ

What is the primary function of the SI5338B-B09791-GMR in a PCIe Gen 4 system?

The SI5338B-B09791-GMR serves as the Common Clock source for PCIe Gen 4 endpoints and root complexes, delivering 100 MHz HCSL clocks with ≤0.45 ps RMS jitter (measured per Intel Clock Jitter Tool v1.6.4). Its factory-programmed B-variant configuration ensures immediate compliance with PCIe Gen 4 Common Clock and Gen 3 SRNS requirements without custom register tuning.

Does the SI5338B-B09791-GMR support crystal oscillator input?

Yes, the SI5338B-B09791-GMR supports 8–30 MHz fundamental-mode crystals directly connected to IN1/IN2 pins. Internal load capacitance is configurable (11–13 pF supported, 17–19 pF recommended), and drive level is limited to 100 µW to ensure crystal reliability across temperature and aging.

How many independent output frequencies can the SI5338B-B09791-GMR generate simultaneously?

The SI5338B-B09791-GMR can generate four independent output frequencies simultaneously - one per output pair (CLK0A/B through CLK3A/B). Two frequencies above 350 MHz (e.g., Fvco/4 and Fvco/6) may be active concurrently, but higher-frequency outputs share the same VCO stage and require integer-related synthesis.

What output voltage levels does the SI5338B-B09791-GMR support per channel?

The SI5338B-B09791-GMR supports independent output supply voltages per channel: VDDO0 through VDDO3 each accept 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous LVDS (1.8 V), HCSL (3.3 V), and CMOS (2.5 V) outputs without external level shifters - critical for mixed-interface FPGA designs.

Is ClockBuilder Pro software required to configure the SI5338B-B09791-GMR?

No, ClockBuilder Pro is optional but strongly recommended. The SI5338B-B09791-GMR is fully programmable via standard I²C/SMBus commands; however, ClockBuilder Pro provides GUI-based configuration, PCIe/Ethernet timing validation, and one-click firmware export - significantly reducing bring-up time versus manual register writes.

SI5338B-B09791-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338B-B09791-GMR FAQ

1.How can I place an order for SI5338B-B09791-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B09791-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B09791-GMR reliable?

The price and inventory of SI5338B-B09791-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B09791-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B09791-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B09791-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B09791-GMR?

SI5338B-B09791-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B09791-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B09791-GMR?

For technical support, including SI5338B-B09791-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B09791-GMR requirements.

6.How does Aetrix verify that SI5338B-B09791-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B09791-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B09791-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B09791-GMR?

All SI5338B-B09791-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B09791-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B09791-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B09791-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…