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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B09792-GMR

Name: SI5338B-B09792-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B09792-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B09792-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338B-B09792-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B09792-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B09792-GMR datasheet, SI5338B-B09792-GMR pinout, SI5338B-B09792-GMR application, or SI5338B-B09792-GMR equivalent, key selection criteria include differential output jitter performance, I²C configurability across four independent drivers, PCIe Gen 4 common-clock compliance, spread-spectrum control per output, and 24-QFN package integration with 1.8/2.5/3.3 V core supply compatibility.

Technical Context

The SI5338B-B09792-GMR integrates a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal (8–30 MHz) or CMOS/differential input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode, enabling zero-ppm accuracy and programmable phase offset (±45 ns, <20 ps step).

Output stage flexibility includes per-driver voltage selection (1.5/1.8/2.5/3.3 V), independent format configuration (LVPECL up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz), and glitchless frequency increment/decrement (1 ppm steps) via pin or I²C control. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - Meets PCIe Gen 4 common-clock TJ budget and enables low-bit-error-rate SerDes links.
Output Frequency Range	0.16–710 MHz - Supports all major serial protocols: PCIe, Ethernet (1/10 GbE), Fibre Channel, and broadcast video timing.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - Enables flexible system-level clock tree design without external buffers.
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - Allows direct interfacing to FPGAs, processors, ASICs, and memory interfaces without level-shifting components.
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - Simplifies power domain partitioning in multi-rail systems.
Package	24-pin QFN, 4 × 4 mm - Enables high-density PCB layouts while maintaining thermal resistance θJA = 37 °C/W.
Operating Temperature	–40 to +85 °C - Qualified for industrial and telecom line-card environments.

Pinout & Package

The SI5338B-B09792-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks' Si5338 family specification and validated for signal integrity and thermal performance.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination for optimal jitter.
IN3/IN4	Single-ended CMOS inputs	Support 5–200 MHz DC-coupled clocks; VIH/VIL referenced to VDD; slew rate >1 V/ns required for low jitter.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair configurable for format, voltage, and termination.
VDDO0–VDDO3	Per-output buffer supplies	Enable independent voltage setting (1.5/1.8/2.5/3.3 V) per driver-critical for mixed-voltage SoC/FPGA interfaces.
SCL/SDA	I²C interface	Standard SMBus-compatible 100 kHz/400 kHz bus for full register configuration, including MultiSynth dividers and SSC parameters.
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock or loss-of-signal; simplifies system-level fault detection without polling.

Key Features

Feature	Design Value
Independent MultiSynth™ synthesis per output	Enables true zero-ppm frequency accuracy on all four outputs simultaneously-eliminates need for multiple discrete oscillators.
Programmable spread spectrum (SSC)	Configurable per output: 0.5–5.0% spread, 33–63 kHz modulation rate-reduces EMI in dense PCB layouts without affecting timing margins.
Glitchless frequency adjustment	1 ppm step size via PINC/FDEC pins or I²C-allows dynamic clock scaling in real-time applications like adaptive video processing.
Sub-20 ps phase step resolution	Enables precise skew alignment between high-speed SerDes lanes (e.g., PCIe x16 or 10 GbE XAUI) without external delay lines.
External feedback mode	Supports zero-delay operation for clock distribution networks-maintains deterministic latency between input and output clocks.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 switch ICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical, low-jitter (0.15–0.45 ps RMS) PCIe-compliant clocks with matched propagation delay. Use Value: Ensures Gen 4 link training success and maintains BER <10⁻¹² across all lanes without requiring individual oscillator placement near each switch.	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10 GbE PHYs and packet processors in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count by replacing three discrete oscillators while maintaining sub-1 ps RMS jitter required for 10GBASE-R FEC tolerance.
Broadcast Video Frame Sync	FPGA-Based Video Processing
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS and HCSL outputs at SMPTE ST 2082/ST 2081 rates with programmable phase offset. Use Value: Enables frame-accurate switching between sources by aligning output edges within ±20 ps-critical for seamless video transitions.	Use Scenario: Supplying 300 MHz DDR4 memory clock, 250 MHz transceiver reference, and 100 MHz logic clock to a Xilinx Versal FPGA in a vision AI edge node. IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO per output driving mixed-voltage FPGA domains (1.2 V, 1.8 V, 2.5 V). Use Value: Eliminates inter-domain noise coupling by isolating power rails per clock domain-improves signal integrity and reduces timing closure effort.

PCIe Gen 4 Switch Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 switch ICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical, low-jitter (0.15–0.45 ps RMS) PCIe-compliant clocks with matched propagation delay.

Use Value: Ensures Gen 4 link training success and maintains BER <10⁻¹² across all lanes without requiring individual oscillator placement near each switch.

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10 GbE PHYs and packet processors in a Layer 3 switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae-compliant frequencies from a single 25 MHz crystal reference.

Use Value: Reduces BOM count by replacing three discrete oscillators while maintaining sub-1 ps RMS jitter required for 10GBASE-R FEC tolerance.

Broadcast Video Frame Sync

FPGA-Based Video Processing

Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, receivers, and frame synchronizers in broadcast infrastructure.

IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS and HCSL outputs at SMPTE ST 2082/ST 2081 rates with programmable phase offset.

Use Value: Enables frame-accurate switching between sources by aligning output edges within ±20 ps-critical for seamless video transitions.

Use Scenario: Supplying 300 MHz DDR4 memory clock, 250 MHz transceiver reference, and 100 MHz logic clock to a Xilinx Versal FPGA in a vision AI edge node.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO per output driving mixed-voltage FPGA domains (1.2 V, 1.8 V, 2.5 V).

Use Value: Eliminates inter-domain noise coupling by isolating power rails per clock domain-improves signal integrity and reduces timing closure effort.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B09792-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration-B09792 variant uses preloaded firmware for specific frequency plan.	Identical use cases; no functional difference in field programming capability or performance specs.	Select B09792-GMR variants when pre-validated clock tree configuration is required to reduce bring-up time.
LMK04832RHAR	Two PLLs + eight outputs; higher power (120 mA typ); supports JESD204B subclass 1; no integrated crystal driver.	Better suited for RF/data converter timing where deterministic latency and dual-loop clean-up are critical.	Choose LMK04832RHAR only when JESD204B deterministic latency or ultra-low additive jitter (<0.1 ps RMS) is mandatory.

Compared with Si5338A-B09792-GMR, the SI5338B-B09792-GMR offers identical hardware functionality but ships with updated factory firmware supporting enhanced PCIe Gen 4 SRNS compliance testing modes; versus LMK04832RHAR, it provides lower power, smaller footprint, and integrated crystal drive-but lacks dual-loop jitter cleaning for ADC/DAC clocking.

Availability

SI5338B-B09792-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE synchronization, broadcast video frame sync, and FPGA-based video processing requiring stable component supply and long-term production continuity.

Supply support for SI5338B-B09792-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-while maintaining sub-picosecond jitter performance.

FAQ

What is the maximum output frequency supported by SI5338B-B09792-GMR in LVPECL format?

The SI5338B-B09792-GMR supports LVPECL outputs up to 710 MHz. This capability is verified in Table 6 of the datasheet under "Output Clocks (Differential)" and enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10 GbE PHYs without frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints.

Does SI5338B-B09792-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338B-B09792-GMR meets PCIe Gen 4 SRNS requirements with 0.11–0.32 ps RMS jitter (typ) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This is explicitly confirmed in Table 12's "PCIe Gen 3 Separate Reference No Spread, SRNS" and "PCIe Gen 4, Common Clock" entries, both referencing the same device family and test conditions.

Can SI5338B-B09792-GMR generate four different output frequencies simultaneously?

Yes, SI5338B-B09792-GMR synthesizes four independent frequencies simultaneously using its four MultiSynth™ engines. Each output supports any frequency from 0.16 MHz to 710 MHz (depending on format), with zero-ppm precision and independent format/voltage configuration-enabling heterogeneous clock trees from a single device.

What input reference options does SI5338B-B09792-GMR support?

SI5338B-B09792-GMR accepts multiple input references: external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz). All inputs are validated per Table 6 and support automatic loss-of-signal detection with configurable release time (0.01–1 µs).

Is SI5338B-B09792-GMR pin-compatible with other Si5338 variants?

Yes, all Si5338 variants-including SI5338B-B09792-GMR-are mechanically and electrically pin-compatible across the family. The 24-QFN package, pin functions (e.g., CLK0A–CLK3B, IN1–IN6, SCL/SDA), and power domains (VDD, VDDO0–VDDO3) are identical; only factory-programmed NVM content differs between A/B/C suffixes.

SI5338B-B09792-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338B-B09792-GMR FAQ

1.How can I place an order for SI5338B-B09792-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B09792-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B09792-GMR reliable?

The price and inventory of SI5338B-B09792-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B09792-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B09792-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B09792-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B09792-GMR?

SI5338B-B09792-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B09792-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B09792-GMR?

For technical support, including SI5338B-B09792-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B09792-GMR requirements.

6.How does Aetrix verify that SI5338B-B09792-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B09792-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B09792-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B09792-GMR?

All SI5338B-B09792-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B09792-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B09792-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B09792-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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