Skyworks Solutions Inc. SI5338B-B11485-GMR
- Part No.:
- SI5338B-B11485-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338B-B11485-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338B-B11485-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338B-B11485-GMR datasheet, SI5338B-B11485-GMR pinout, SI5338B-B11485-GMR application, or SI5338B-B11485-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338B-B11485-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode with <20 ps phase step resolution and 1 ppm frequency increment/decrement.
Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, independent VDDO supplies, and optional spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation). The device supports zero-delay mode via external feedback and includes loss-of-lock and loss-of-signal alarms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements at 100 MHz HCSL output |
| Output Frequency Range | 0.16–710 MHz - covers PCIe (100/125 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and broadcast video (27/74.25/148.5 MHz) |
| Input Reference Support | 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - enables flexible system clock sourcing without external buffers |
| Supply Voltages | VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows mixed-voltage board designs and level translation between FPGA I/O banks and SerDes receivers |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard reflow profiles and supports high-density routing with exposed thermal pad |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments without derating |
Pinout & Package
SI5338B-B11485-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, RoHS-compliant, MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support 5–200 MHz CMOS inputs; VIH/VIL referenced to local VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential output pairs | Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply |
| VDDO0–VDDO3 | Output buffer supplies | Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for interfacing with mixed-voltage receivers |
| SCL, SDA | I²C interface | Standard SMBus-compatible 2-wire bus; supports 100/400 kHz modes; no pull-ups required on device side |
| INTR | Interrupt output | Open-drain status flag for loss-of-lock or loss-of-signal events; active-low, 3 mA sink capability |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals or trimming components |
| Independent output voltage per driver | Allows direct connection to diverse receivers (e.g., 1.8 V FPGA bank, 3.3 V microcontroller, 2.5 V PHY) without external level shifters |
| Glitchless frequency adjustment | 1 ppm step size with pin-controlled increment/decrement enables real-time clock tuning during system operation without output interruption |
| Programmable phase offset | ±45 ns range in <20 ps steps permits precise skew alignment across multi-lane interfaces like PCIe or DDR memory channels |
| Spread-spectrum modulation | Configurable down-spread (0.5–5.0%) at 33–63 kHz reduces EMI peak emissions for FCC/CE compliance without affecting timing margin |
Applications
| PCIe Gen 3/4 Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe root complexes and endpoints in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock topology with Gen 3 SRNS and Gen 4 jitter compliance. Use Value: Eliminates four discrete oscillators while maintaining sub-0.45 ps RMS jitter required for PCIe Gen 4 link training stability. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and switch fabric ASICs. IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting IEEE 802.3 standards with independent output format and voltage control. Use Value: Enables single-device clock tree for multi-rate Ethernet platforms, reducing BOM count and layout complexity. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 74.25 MHz and ST 2081 (6G-SDI) 148.5 MHz clocks with ultra-low jitter to serializer/deserializer ICs. IC Role / Device Role / Timing Role: Low-phase-jitter clock source meeting SMPTE RP 184 jitter mask requirements for uncompressed video transport. Use Value: Achieves 0.7 ps RMS jitter at 148.5 MHz-well below the 1.5 ps RMS limit-ensuring bit-error-free transmission over long coaxial runs. | Use Scenario: Supplying core, I/O, and peripheral clocks to Xilinx Versal or Intel Agilex FPGAs with mixed-voltage I/O banks. IC Role / Device Role / Timing Role: Configurable clock generator with per-output VDDO and format selection for heterogeneous FPGA clock domains. Use Value: Replaces multiple fixed-frequency oscillators and level translators, simplifying power sequencing and reducing PCB layer count. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B11485-GMR | Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant) | Identical functional scope; B variant includes pre-loaded PCIe Gen 4 timing profile | Select SI5338B-B11485-GMR when PCIe Gen 4 SRNS compliance is required out-of-box |
| LMK04832ISQE/NOPB | Two PLLs + eight outputs; higher power (90 mA); supports JESD204B deterministic latency | Targeted at RF/data converter timing; lacks integrated crystal oscillator support | Choose LMK04832 for JESD204B systems requiring sub-ns synchronization; SI5338B-B11485-GMR preferred for cost-sensitive PCIe/Ethernet applications |
Compared with Si5338A-B11485-GMR, SI5338B-B11485-GMR delivers identical hardware functionality but ships with PCIe Gen 4-optimized firmware; versus LMK04832, it offers lower power and integrated crystal support at the expense of JESD204B features.
Availability
SI5338B-B11485-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, 10 GbE switch fabrics, and broadcast video equipment requiring stable component supply, full traceability, and long-term lifecycle support.
Supply support for SI5338B-B11485-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in data center, networking, and broadcast systems where low jitter, flexible frequency synthesis, and compact footprint are critical.
FAQ
What is the primary function of the SI5338B-B11485-GMR in a PCIe Gen 4 system?
The SI5338B-B11485-GMR serves as the common reference clock generator for PCIe Gen 4 root complexes and endpoints, delivering four low-jitter (≤0.45 ps RMS) 100 MHz outputs compliant with PCIe Gen 4 SRNS specifications. Its MultiSynth™ architecture ensures zero-ppm frequency accuracy and supports spread-spectrum modulation to reduce EMI without violating jitter limits. SI5338B-B11485-GMR integrates this functionality into a single 4 × 4 mm QFN package, replacing multiple discrete oscillators.
Does the SI5338B-B11485-GMR support crystal oscillator input, and what frequency range is validated?
Yes, the SI5338B-B11485-GMR supports fundamental-mode parallel-resonant crystals from 8 to 30 MHz, with validated performance across four bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band specifies supported and recommended load capacitance (11–13 pF supported, 17–19 pF recommended), maximum ESR (75–300 Ω), and drive level (≤100 µW). SI5338B-B11485-GMR includes on-chip capacitors and register-adjustable settings for optimal crystal biasing.
How does the SI5338B-B11485-GMR achieve independent output voltage control, and why is it important?
The SI5338B-B11485-GMR provides four dedicated VDDOx supply pins (VDDO0–VDDO3), each powering one output driver pair and configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V operation. This enables direct interfacing with mixed-voltage receivers-such as 1.8 V FPGA I/O banks, 2.5 V SerDes lanes, and 3.3 V microcontrollers-without external level shifters. SI5338B-B11485-GMR thus simplifies power domain partitioning and eliminates signal integrity degradation from passive translation circuits.
Can the SI5338B-B11485-GMR generate frequencies above 350 MHz, and what are the constraints?
Yes, the SI5338B-B11485-GMR supports output frequencies up to 710 MHz, but only two unique frequencies above 350 MHz may be generated simultaneously-specifically Fvco/4 and Fvco/6-due to VCO frequency division constraints. Frequencies from 367–473.33 MHz and 550–710 MHz are supported for LVPECL/LVDS/CML outputs. SI5338B-B11485-GMR requires careful MultiSynth™ register configuration to avoid aliasing and ensure phase noise remains within specification across all active outputs.
What software tools are officially supported for programming the SI5338B-B11485-GMR?
Skyworks provides ClockBuilder Pro-a free, GUI-based configuration tool-for designing, simulating, and generating register maps for the SI5338B-B11485-GMR. It supports I²C programming, jitter analysis, and export to C header files or EEPROM images. SI5338B-B11485-GMR also integrates with the Skyworks PCIe Clock Jitter Tool for automated compliance testing against PCIe Gen 1–4 specifications. No third-party tools are required for full functionality.
SI5338B-B11485-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- PLL:
- Yes with Bypass
- Main Purpose:
- Ethernet, Fibre Channel, PCI Express (PCIe), Telecom
- Input:
- CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal
- Output:
- CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 3:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 350MHz
- Voltage - Supply:
- 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338B-B11485-GMR FAQ
1.How can I place an order for SI5338B-B11485-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338B-B11485-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338B-B11485-GMR reliable?
The price and inventory of SI5338B-B11485-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B11485-GMR is usually 5 days.
3.What payment methods are accepted for SI5338B-B11485-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B11485-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338B-B11485-GMR?
SI5338B-B11485-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338B-B11485-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338B-B11485-GMR?
For technical support, including SI5338B-B11485-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B11485-GMR requirements.
6.How does Aetrix verify that SI5338B-B11485-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338B-B11485-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B11485-GMR meets industry standards.
7.What is the process for return or replacement of SI5338B-B11485-GMR?
All SI5338B-B11485-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B11485-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338B-B11485-GMR part is unused and in its original packaging.
Return procedure for SI5338B-B11485-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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