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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B11486-GMR

Name: SI5338B-B11486-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B11486-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B11486-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B11486-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B11486-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B11486-GMR datasheet, SI5338B-B11486-GMR pinout, SI5338B-B11486-GMR application, or SI5338B-B11486-GMR equivalent, key selection criteria include PCIe jitter compliance, independent per-output voltage (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained FPGA/ASIC clock trees.

Technical Context

The SI5338B-B11486-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each feeding a configurable output driver. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output supports independent frequency, format, voltage, phase offset (±45 ns, <20 ps step), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation). Loss-of-lock and loss-of-signal alarms, I²C/SMBus interface, and zero-delay mode via external feedback are integrated.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements at 100 MHz HCSL output
Output Frequency Range	0.16–710 MHz - covers PCIe (100 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and processor clocks
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - enables direct interfacing to FPGAs, ASICs, SerDes PHYs, and memory controllers without level-shifting
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports mixed-voltage system design and low-power operation (45 mA typ core current)
Synthesis Resolution	1 ppb - enables exact frequency generation (e.g., 156.25 MHz ±0 Hz) for deterministic jitter-sensitive protocols like CPRI and OTN
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating
Package	24-pin QFN, 4 × 4 mm - compatible with standard PCB assembly processes and thermal management in dense routing layouts

Pinout & Package

SI5338B-B11486-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, RoHS-compliant, MSL3.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDO supply
VDDO0–VDDO3	Output buffer supplies	Enable independent voltage setting (1.5/1.8/2.5/3.3 V) per output pair for mixed-interface systems
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz control bus; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events
VDD	Core supply	1.8/2.5/3.3 V core power; PSRR optimized for noisy digital environments
GND, RSVD_GND	Ground terminals	Multiple GND pins and dedicated reserved ground reduce ground bounce and improve jitter performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs simultaneously
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode satisfies Intel's strict jitter floor for Gen 3 root complex timing
Independent phase adjustment	±45 ns range with <20 ps step size allows precise skew alignment between SerDes lanes or DDR strobes
Glitchless frequency tuning	1 ppm increment/decrement via PINC/FDEC pins enables real-time dynamic frequency scaling without output interruption
Configurable spread spectrum	Programmable 0.5–5.0% down-spread at 33–63 kHz reduces EMI peak emissions in compact PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE Line Card
Use Scenario: High-density PCIe Gen 4 switch fabric requiring four synchronized 100 MHz clocks with sub-0.5 ps RMS jitter for upstream/downstream ports and management controller. IC Role / Device Role / Timing Role: Primary clock generator providing PCIe Common Clock (CC) and separate reference for CDR circuits; configured in integer synthesis mode for lowest jitter. Use Value: Meets PCIe Gen 4 total jitter spec (≤33.6 ps pk-pk) while eliminating four discrete oscillators and reducing board area by >60%.	Use Scenario: 10GbE line card with dual XAUI interfaces, MAC controller, and packet processor needing 156.25 MHz, 125 MHz, and 250 MHz clocks with tight inter-output skew. IC Role / Device Role / Timing Role: Quad-output timing hub generating all required frequencies from single 25 MHz crystal reference; uses independent phase offset to align XAUI lane clocks. Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter-enabling IEEE 802.3ae compliance without external jitter cleaners.
Broadcast Video Master Clock	FPGA-Based Telecom Baseband
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz, 74.25 MHz, and 148.5 MHz clocks with deterministic phase relationships. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating exact broadcast frequencies from 27 MHz crystal; uses MultiSynth™ in fractional mode for precise ratios. Use Value: Delivers 0.7 ps RMS jitter and <20 ps phase step resolution-ensuring bit-error-free transmission over long coaxial runs per SMPTE RP 184.	Use Scenario: 5G NR baseband unit with FPGA processing multiple radio channels, requiring 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks with programmable spread spectrum for EMI reduction. IC Role / Device Role / Timing Role: Configurable clock source supporting both fixed and variable-rate sampling clocks; uses independent SSC per output to target different EMI bands. Use Value: Enables FCC Class B compliance in compact outdoor enclosures while maintaining <1 ps RMS jitter for ADC/DAC sampling integrity.

PCIe Gen 4 Switch Timing

Ethernet 10GbE Line Card

Use Scenario: High-density PCIe Gen 4 switch fabric requiring four synchronized 100 MHz clocks with sub-0.5 ps RMS jitter for upstream/downstream ports and management controller.

IC Role / Device Role / Timing Role: Primary clock generator providing PCIe Common Clock (CC) and separate reference for CDR circuits; configured in integer synthesis mode for lowest jitter.

Use Value: Meets PCIe Gen 4 total jitter spec (≤33.6 ps pk-pk) while eliminating four discrete oscillators and reducing board area by >60%.

Use Scenario: 10GbE line card with dual XAUI interfaces, MAC controller, and packet processor needing 156.25 MHz, 125 MHz, and 250 MHz clocks with tight inter-output skew.

IC Role / Device Role / Timing Role: Quad-output timing hub generating all required frequencies from single 25 MHz crystal reference; uses independent phase offset to align XAUI lane clocks.

Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter-enabling IEEE 802.3ae compliance without external jitter cleaners.

Broadcast Video Master Clock

FPGA-Based Telecom Baseband

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz, 74.25 MHz, and 148.5 MHz clocks with deterministic phase relationships.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating exact broadcast frequencies from 27 MHz crystal; uses MultiSynth™ in fractional mode for precise ratios.

Use Value: Delivers 0.7 ps RMS jitter and <20 ps phase step resolution-ensuring bit-error-free transmission over long coaxial runs per SMPTE RP 184.

Use Scenario: 5G NR baseband unit with FPGA processing multiple radio channels, requiring 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks with programmable spread spectrum for EMI reduction.

IC Role / Device Role / Timing Role: Configurable clock source supporting both fixed and variable-rate sampling clocks; uses independent SSC per output to target different EMI bands.

Use Value: Enables FCC Class B compliance in compact outdoor enclosures while maintaining <1 ps RMS jitter for ADC/DAC sampling integrity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08986-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency; requires different programming flow	Targeted at JESD204B-based data converters and multi-channel RF systems where deterministic delay matters more than cost	Select when >4 outputs or sub-0.5 ps jitter is mandatory; not drop-in due to pin count (40-QFN) and register map differences
ICS8430I-01T	Fixed-frequency quad LVDS generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only; 32-TQFP package	Suitable for legacy designs with static clock trees and no need for field reconfiguration or voltage flexibility	Choose for cost-sensitive, low-complexity applications where frequency agility and multi-voltage support are unnecessary

Compared with SI5338B-B11486-GMR, Si5332A-D08986-GM offers superior jitter and scalability but increases BOM cost and layout complexity, while ICS8430I-01T sacrifices programmability and flexibility for simplicity and lower unit price in static timing architectures.

Availability

SI5338B-B11486-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line cards, broadcast video master clocking, and FPGA-based telecom baseband applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338B-B11486-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable any-frequency clock generation for high-speed serial interfaces, designed specifically to replace multiple fixed-frequency oscillators in PCIe, Ethernet, Fibre Channel, and broadcast video systems.

FAQ

What is the maximum output frequency supported by SI5338B-B11486-GMR in LVPECL format?

The SI5338B-B11486-GMR supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the official datasheet. This capability enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10GbE PHYs without frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints within the MultiSynth™ architecture.

Does SI5338B-B11486-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338B-B11486-GMR meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS jitter (Table 12), measured at 100 MHz HCSL output under specified PLL bandwidth (2–4 or 2–5 MHz) and CDR conditions (10 MHz). This compliance is explicitly stated in the Features section and verified using the Skyworks PCIe Clock Jitter Tool per AN562.

Can SI5338B-B11486-GMR generate four different output frequencies simultaneously?

Yes, SI5338B-B11486-GMR synthesizes four independent frequencies simultaneously using its four MultiSynth™ engines. Each output driver supports fully independent configuration-including frequency, format, voltage, phase offset, and spread-spectrum parameters-enabling true any-frequency, any-output operation without shared dividers or constraints.

What input reference options are supported by SI5338B-B11486-GMR?

SI5338B-B11486-GMR accepts multiple reference types: external crystal (8–30 MHz), CMOS single-ended (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). The device auto-detects input type and configures internal termination accordingly, enabling flexible system-level clock tree design without external conditioning circuitry.

Is ClockBuilder Pro software required to configure SI5338B-B11486-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338B-B11486-GMR configuration. The device supports full I²C/SMBus register-level programming, but ClockBuilder Pro provides validated GUI-based setup, jitter optimization, pin assignment validation, and exportable configuration files-reducing development time and ensuring compliance with PCIe, Ethernet, and broadcast timing standards.

SI5338B-B11486-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Voltage - Supply:: 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B11486-GMR FAQ

1.How can I place an order for SI5338B-B11486-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B11486-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B11486-GMR reliable?

The price and inventory of SI5338B-B11486-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B11486-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B11486-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B11486-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B11486-GMR?

SI5338B-B11486-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B11486-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B11486-GMR?

For technical support, including SI5338B-B11486-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B11486-GMR requirements.

6.How does Aetrix verify that SI5338B-B11486-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B11486-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B11486-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B11486-GMR?

All SI5338B-B11486-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B11486-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B11486-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B11486-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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