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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04068-GM

Name: SI5338C-B04068-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04068-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04068-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04068-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04068-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL outputs. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe Gen4 root complexes.

For engineers reviewing the SI5338C-B04068-GM datasheet, SI5338C-B04068-GM pinout, SI5338C-B04068-GM application, or SI5338C-B04068-GM equivalent, key selection criteria include differential output jitter performance (0.11–0.45 ps RMS for PCIe Gen3/Gen4 SRNS), independent per-output voltage control (1.5–3.3 V), and programmable phase/frequency adjustment in 20 ps / 1 ppm steps.

Technical Context

The SI5338C-B04068-GM integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths. Each output driver supports configurable format, voltage, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).

It operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and offers loss-of-lock and loss-of-signal alarms via the INTR pin. The device supports both free-running clock generation and synchronous frequency translation modes, with external feedback enabling zero-delay operation.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); enables PCIe Gen4 Common Clock compliance
Frequency range	0.16–710 MHz per output; supports integer/fractional synthesis with 1 ppb resolution
Input flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3
Temperature range	–40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment

Pinout & Package

SI5338C-B04068-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), eight output terminals (CLK0A/B–CLK3A/B), four VDDOx supplies, dual VDD core rails, SCL/SDA/I²C interface, INTR alarm, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled 5–710 MHz differential signals; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support DC-coupled CMOS/SSTL/HSTL at 5–350 MHz; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B (x4 pairs)	Differential clock outputs	Configurable per-output format (LVPECL/LVDS/HCSL/CML); each pair shares VDDOx supply rail
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output group; enable mixed-voltage system interfacing
VDD (pins 9,10)	Core supply	Single 1.8/2.5/3.3 V supply for PLL, logic, and memory; PSRR optimized for noise immunity
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal events; active-low assertion

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs simultaneously
PCIe Gen3/Gen4 SRNS compliance	0.11 ps RMS jitter (Gen3 SRNS) and 0.15 ps RMS (Gen4 Common Clock) meet Intel specification requirements
Per-output voltage control	Each output group (CLK0–CLK3) has dedicated VDDOx rail, allowing mixed-interface systems (e.g., 1.8 V FPGA + 3.3 V PHY)
Programmable phase offset	±45 ns initial phase adjustment with <20 ps step resolution for skew alignment across high-speed SerDes lanes
Glitchless frequency tuning	Independent ±1 ppm frequency increment/decrement via pin or I²C, enabling dynamic clock scaling without output interruption
Spread spectrum modulation	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts

Applications

PCIe Gen4 Root Complex Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen4 endpoints and switch fabric in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent spread-spectrum control per lane. Use Value: Meets PCIe Gen4 Common Clock jitter spec (0.15 ps RMS) while enabling EMI reduction via per-output SSC-eliminating need for discrete spread-spectrum oscillators.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in a layer-3 switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing multiple fixed-frequency XO modules with a single programmable device. Use Value: Reduces BOM count by 4× and board space by >60% versus discrete oscillators; supports field-upgradable clock plans via I²C.
FPGA and Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying 200 MHz system clock, 500 MHz transceiver reference, and two auxiliary clocks to a Xilinx Versal ACAP with mixed-voltage I/O banks. IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8 V/2.5 V/3.3 V) and format (LVDS/HCSL/CMOS) selection. Use Value: Eliminates level-shifting circuitry and discrete buffers; simplifies power domain partitioning across heterogeneous FPGA subsystems.	Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks and genlock signals to video processing FPGAs and serializer ICs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) clock generator supporting precise frame synchronization and jitter-critical pixel clock recovery. Use Value: Enables sub-100 fs timing margin for 27 Gbps CDR lock; meets SMPTE ST 2059-2 PTP grandmaster timing stability requirements.

PCIe Gen4 Root Complex Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen4 endpoints and switch fabric in a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent spread-spectrum control per lane.

Use Value: Meets PCIe Gen4 Common Clock jitter spec (0.15 ps RMS) while enabling EMI reduction via per-output SSC-eliminating need for discrete spread-spectrum oscillators.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in a layer-3 switch ASIC.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing multiple fixed-frequency XO modules with a single programmable device.

Use Value: Reduces BOM count by 4× and board space by >60% versus discrete oscillators; supports field-upgradable clock plans via I²C.

FPGA and Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying 200 MHz system clock, 500 MHz transceiver reference, and two auxiliary clocks to a Xilinx Versal ACAP with mixed-voltage I/O banks.

IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8 V/2.5 V/3.3 V) and format (LVDS/HCSL/CMOS) selection.

Use Value: Eliminates level-shifting circuitry and discrete buffers; simplifies power domain partitioning across heterogeneous FPGA subsystems.

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks and genlock signals to video processing FPGAs and serializer ICs in 4K/8K broadcast equipment.

IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) clock generator supporting precise frame synchronization and jitter-critical pixel clock recovery.

Use Value: Enables sub-100 fs timing margin for 27 Gbps CDR lock; meets SMPTE ST 2059-2 PTP grandmaster timing stability requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04083-GM	Same Si5338 family; factory-programmed with different default configuration (e.g., output formats, frequencies, SSC settings)	Pre-configured for specific OEM reference designs; requires no initial I²C programming	Select when pre-loaded firmware reduces bring-up time and eliminates need for ClockBuilder Pro setup
LMK04832RHAT	Two-stage jitter cleaner with integrated LDOs; higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency	Targeted at RF/data converter timing where sub-100 fs additive jitter and deterministic delay are critical	Select when ultra-low additive jitter (<0.1 ps RMS) and deterministic latency outweigh cost and size constraints

Compared with Si5338A-B04083-GM, SI5338C-B04068-GM offers full field programmability but requires ClockBuilder Pro configuration; compared with LMK04832RHAT, it provides lower power and smaller footprint but lacks jitter cleaning and deterministic latency features.

Availability

SI5338C-B04068-GM is available at Aetrix Electronics and suitable for PCIe Gen4 timing, Ethernet switch/router clocking, and FPGA processor clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B04068-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, multi-protocol clock generation in datacenter, networking, and broadcast infrastructure-enabling consolidation of discrete oscillators into a single, software-defined timing IC.

FAQ

What is the maximum output frequency supported by the SI5338C-B04068-GM?

The SI5338C-B04068-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints. All outputs maintain 0.7 ps RMS typical phase jitter within their respective ranges.

Does the SI5338C-B04068-GM support PCIe Gen4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338C-B04068-GM is compliant with PCIe Gen4 SRNS requirements, delivering 0.11–0.32 ps RMS jitter (1.5 MHz–50 MHz band) when configured with PLL bandwidth of 2–5 MHz and CDR = 10 MHz. This is verified per PCI-SIG Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool.

How is the SI5338C-B04068-GM programmed, and what tools are required?

The SI5338C-B04068-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. This GUI-based tool enables full register configuration-including output format, frequency, voltage, phase, and spread-spectrum parameters-and generates custom configuration files for one-time OTP programming or runtime loading. No external hardware programmer is needed beyond a USB-to-I²C adapter.

Can the SI5338C-B04068-GM operate with a single-ended input clock?

Yes, the SI5338C-B04068-GM accepts single-ended CMOS, SSTL, or HSTL inputs on pins IN3 and IN4 across 5–350 MHz. Input thresholds are referenced to VDD (VIH = 0.7×VDD, VIL = 0.3×VDD), and slew rate should exceed 1 V/ns for optimal jitter performance. Differential inputs remain available on IN1/IN2 and IN5/IN6 for higher-noise environments.

What thermal considerations apply to the SI5338C-B04068-GM in continuous operation?

The SI5338C-B04068-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At full load (45 mA core current, 30 mA per active LVPECL output), power dissipation reaches ~180 mW. A minimum 40 mm² copper pour under the exposed thermal pad is recommended to maintain junction temperature ≤115 °C at +85 °C ambient-ensuring reliable operation over full industrial temperature range.

SI5338C-B04068-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04068-GM FAQ

1.How can I place an order for SI5338C-B04068-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04068-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04068-GM reliable?

The price and inventory of SI5338C-B04068-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04068-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B04068-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04068-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04068-GM?

SI5338C-B04068-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04068-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04068-GM?

For technical support, including SI5338C-B04068-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04068-GM requirements.

6.How does Aetrix verify that SI5338C-B04068-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04068-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04068-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B04068-GM?

All SI5338C-B04068-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04068-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04068-GM part is unused and in its original packaging.

Return procedure for SI5338C-B04068-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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