Skyworks Solutions Inc. SI5338C-B04167-GMR
- Part No.:
- SI5338C-B04167-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B04167-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,950
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Product details
Overview
SI5338C-B04167-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338C-B04167-GMR datasheet, SI5338C-B04167-GMR pinout, SI5338C-B04167-GMR application, or SI5338C-B04167-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and support for differential input frequencies up to 710 MHz.
Technical Context
The SI5338C-B04167-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each output supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), phase offset (±45 ns), and frequency increment/decrement (1 ppm steps).
It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and I²C/SMBus-compatible configuration via 24-bit address space. The device integrates one-time-programmable (OTP) NVM for factory or field programming, enabling deterministic startup without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | Four independent clock outputs (CLK0A/B through CLK3A/B) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock specs |
| Frequency range | 0.16–710 MHz per output; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz |
| Input reference | Differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal |
| Supply voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp. | –40 °C to +85 °C ambient; qualified per industrial temperature grade |
Pinout & Package
The SI5338C-B04167-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are standardized across the Si5338 family and validated per Skyworks Rev. 1.6 datasheet, page 33 (Pin Descriptions) and page 37 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs | Eight terminals supporting four differential outputs; each pair configurable for LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing |
| SCL, SDA | I²C interface | Standard SMBus-compatible 2-wire bus (up to 400 kHz); supports multi-drop configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration errors |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with true zero-ppm accuracy on all outputs |
| Programmable spread spectrum | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in noise-sensitive systems |
| Independent phase control | ±45 ns programmable initial phase offset and <20 ps step resolution for skew compensation across multiple clock domains |
| Glitchless frequency tuning | Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption |
| Flexible input architecture | Supports six input types - crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (<0.45 ps RMS) HCSL clocks compliant with PCIe Gen 4 Common Clock specification. Use Value: Eliminates need for four discrete oscillators; enables deterministic inter-lane skew control via independent phase adjustment per output. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in enterprise Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board area; supports dynamic reconfiguration for multi-rate port provisioning without hardware change. |
| Broadcast Video Sync | FPGA-Based Test Equipment |
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, video processors, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) clock source meeting SMPTE ST 2082-1 jitter requirements for 12G-SDI. Use Value: Enables deterministic phase alignment across video processing pipelines using programmable initial phase offset and fine-grained phase stepping. |
Use Scenario: Supplying multiple precisely timed clocks (e.g., 100 MHz system clock, 200 MHz ADC sampling clock, 500 MHz FPGA transceiver reference) in automated test equipment. IC Role / Device Role / Timing Role: Configurable quad clock generator supporting mixed-signal test instrumentation requiring independent frequency, format, and voltage per subsystem. Use Value: Allows single-device timing solution for heterogeneous FPGA peripherals; simplifies layout with pin-selectable output enables and spread-spectrum EMI reduction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B-GM | Same silicon die and pinout; differs only in factory-programmed OTP configuration (predefined frequency plan vs. blank OTP in SI5338C-B04167-GMR) | Pre-configured for fixed-frequency use cases; lacks field-programmability of SI5338C-B04167-GMR's blank OTP | Select SI5338C-B04167-GMR when full I²C programmability and custom frequency plans are required at production or field level. |
| LMK04832ISQE/NOPB | Two-stage jitter cleaner with integrated dual-loop PLL; higher power (120 mA typ), larger 36-QFN package; supports JESD204B SYSREF | Targeted at RF/data converter timing with ultra-low additive jitter (<50 fs); not optimized for PCIe or Ethernet clock tree replacement | Choose LMK04832ISQE/NOPB only when sub-100 fs additive jitter or deterministic SYSREF distribution is mandatory; SI5338C-B04167-GMR offers better cost, size, and integration for general-purpose clock synthesis. |
Compared with Si5338A-B-GM, SI5338C-B04167-GMR provides full field programmability via I²C and blank OTP, enabling late-stage design flexibility; compared with LMK04832ISQE/NOPB, it delivers lower system cost and smaller footprint at the expense of ultra-low additive jitter performance required in RF sampling applications.
Availability
SI5338C-B04167-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video sync applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338C-B04167-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products for communications, automotive, and industrial markets.
The Si5338 product line was designed as a highly configurable, low-jitter clock generator family targeting high-speed serial interface timing in networking, computing, and broadcast infrastructure where multi-frequency synthesis and PCIe/Ethernet compliance are critical.
FAQ
What is the primary function of the SI5338C-B04167-GMR?
The SI5338C-B04167-GMR is an I²C-programmable quad clock generator IC that synthesizes up to four independent, low-jitter output clocks from a single input reference. It uses Skyworks' MultiSynth™ technology to deliver any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, making it suitable for PCIe Gen 4, Ethernet, and broadcast video timing applications. Its blank OTP allows full field configuration.
Does the SI5338C-B04167-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338C-B04167-GMR meets PCIe Gen 4 Common Clock specifications with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. It supports the required 100 MHz HCSL output format and complies with Gen 4 jitter masks under specified PLL bandwidth (2–5 MHz) and CDR (10 MHz) conditions.
How many input reference sources does the SI5338C-B04167-GMR support?
The SI5338C-B04167-GMR supports six distinct input reference configurations: differential (IN1/IN2, IN5/IN6), single-ended CMOS (IN3/IN4), SSTL/HSTL (IN3/IN4), and external crystal (8–30 MHz). Each input path includes dedicated signal conditioning and loss-of-signal detection circuitry.
Can output voltage levels be set independently per channel on the SI5338C-B04167-GMR?
Yes, the SI5338C-B04167-GMR provides four independent VDDOx supplies (VDDO0–VDDO3), allowing each output bank to be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA banks and 3.3 V legacy peripherals) without external level shifters.
Is the SI5338C-B04167-GMR pin-compatible with other Si5338 variants?
Yes, all Si5338 variants-including SI5338C-B04167-GMR-share identical 24-QFN packaging, pinout, and electrical interface. Differences reside solely in factory-programmed OTP content or blankness; no PCB layout changes are needed when migrating between Si5338A, Si5338B, or Si5338C variants.
SI5338C-B04167-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B04167-GMR FAQ
1.How can I place an order for SI5338C-B04167-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B04167-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B04167-GMR reliable?
The price and inventory of SI5338C-B04167-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04167-GMR is usually 5 days.
3.What payment methods are accepted for SI5338C-B04167-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04167-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B04167-GMR?
SI5338C-B04167-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B04167-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B04167-GMR?
For technical support, including SI5338C-B04167-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04167-GMR requirements.
6.How does Aetrix verify that SI5338C-B04167-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338C-B04167-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04167-GMR meets industry standards.
7.What is the process for return or replacement of SI5338C-B04167-GMR?
All SI5338C-B04167-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04167-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B04167-GMR part is unused and in its original packaging.
Return procedure for SI5338C-B04167-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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