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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04168-GM

Name: SI5338C-B04168-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04168-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04168-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04168-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B04168-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed networking and FPGA timing applications.

For engineers reviewing the SI5338C-B04168-GM datasheet, SI5338C-B04168-GM pinout, SI5338C-B04168-GM application, or SI5338C-B04168-GM equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.

Technical Context

The SI5338C-B04168-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references, followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm accuracy and glitchless frequency adjustment via dedicated control pins or I²C.

Its output stage provides per-driver configurability for signal format, termination, common-mode voltage, and slew rate-critical for maintaining sub-1 ps RMS jitter across mixed-impedance systems. The device supports loss-of-signal and loss-of-lock monitoring, spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation), and zero-delay operation via external feedback mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); enables PCIe Gen 4 Common Clock compliance and low-bit-error-rate serial links
Output Frequency Range	0.16–710 MHz per channel; covers Ethernet (125/156.25/312.5 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz via Fvco/4), and broadcast video (27/74.25 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); allows flexible system-level clock tree design
Output Driver Flexibility	Four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL); supports mixed-signal SoC interfaces without external level translators
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver; simplifies multi-rail board power architecture
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; compatible with standard reflow profiles and high-density PCB layouts
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom line card environments

Pinout & Package

SI5338C-B04168-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept AC-coupled LVPECL/LVDS/HCSL references up to 710 MHz; require external 100 Ω termination
IN3/IN4	Single-ended CMOS/SSTL/HSTL inputs	Support DC-coupled clocks from 5–350 MHz; internal 20 kΩ pull-up/down configurable via register
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent outputs; each pair supports LVPECL/LVDS/HCSL/CML with programmable swing and common-mode voltage
VDDO0–VDDO3	Per-output buffer supply	Enable independent voltage setting (1.5/1.8/2.5/3.3 V) per output driver to match connected IC logic families
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for clean clock generation in noisy power environments
SCL/SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports in-system programming and dynamic frequency updates
INTR	Interrupt output	Open-drain status flag for loss-of-signal, loss-of-lock, or PLL unlock events; enables real-time system monitoring

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with zero-ppm accuracy-no external crystals or VCXOs required
Independent phase adjustment	±45 ns range in <20 ps steps per output; supports precise skew alignment in SerDes and memory interface timing
Glitchless frequency tuning	1 ppm increment/decrement via dedicated pins or I²C; avoids clock interruptions during dynamic rate adaptation
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI without compromising timing margin
PCIe Gen 3 SRNS compliance	Validated 0.11–0.32 ps RMS jitter in Separate Reference No Spread mode; meets Intel specification for root complex and endpoint timing
External feedback mode	Supports zero-delay clock distribution by feeding back a downstream clock to INx; eliminates propagation delay accumulation

Applications

Ethernet Switch Timing	PCIe Gen 4 Clock Distribution
Use Scenario: 10 GbE/25 GbE switch ASIC requiring synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks with tight inter-channel skew. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter outputs-two for SerDes lanes, one for MAC, one for management interface. Use Value: Eliminates four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter critical for IEEE 802.3bj compliance.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, each needing 100 MHz common clock plus separate reference for CDR. IC Role / Device Role / Timing Role: Generates primary 100 MHz common clock (CLK0), secondary 100 MHz reference (CLK1), and two auxiliary clocks (CLK2/CLK3) for BMC and PLX switches. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and SRNS RMS < 0.45 ps; supports simultaneous operation of multiple high-speed peripherals.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082-1 (12G-SDI) router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase stability. IC Role / Device Role / Timing Role: Receives tri-level sync reference on IN3, synthesizes three frame-locked outputs with programmable phase offset for pixel-clock alignment. Use Value: Achieves <20 ps phase step resolution and <0.7 ps RMS jitter-enabling artifact-free 4K/8K video transport without frame tearing.	Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA, requiring multiple precisely timed clocks for stimulus, capture, and DUT interface. IC Role / Device Role / Timing Role: Supplies 200 MHz LVDS for FPGA fabric, 100 MHz HCSL for memory interface, 125 MHz CMOS for microcontroller, and 312.5 MHz LVPECL for SerDes transceivers. Use Value: Single-chip solution replaces four oscillators and level translators; independent voltage per output matches diverse FPGA I/O banks (1.2/1.8/2.5/3.3 V).

Ethernet Switch Timing

PCIe Gen 4 Clock Distribution

Use Scenario: 10 GbE/25 GbE switch ASIC requiring synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks with tight inter-channel skew.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter outputs-two for SerDes lanes, one for MAC, one for management interface.

Use Value: Eliminates four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter critical for IEEE 802.3bj compliance.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, each needing 100 MHz common clock plus separate reference for CDR.

IC Role / Device Role / Timing Role: Generates primary 100 MHz common clock (CLK0), secondary 100 MHz reference (CLK1), and two auxiliary clocks (CLK2/CLK3) for BMC and PLX switches.

Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and SRNS RMS < 0.45 ps; supports simultaneous operation of multiple high-speed peripherals.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082-1 (12G-SDI) router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase stability.

IC Role / Device Role / Timing Role: Receives tri-level sync reference on IN3, synthesizes three frame-locked outputs with programmable phase offset for pixel-clock alignment.

Use Value: Achieves <20 ps phase step resolution and <0.7 ps RMS jitter-enabling artifact-free 4K/8K video transport without frame tearing.

Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA, requiring multiple precisely timed clocks for stimulus, capture, and DUT interface.

IC Role / Device Role / Timing Role: Supplies 200 MHz LVDS for FPGA fabric, 100 MHz HCSL for memory interface, 125 MHz CMOS for microcontroller, and 312.5 MHz LVPECL for SerDes transceivers.

Use Value: Single-chip solution replaces four oscillators and level translators; independent voltage per output matches diverse FPGA I/O banks (1.2/1.8/2.5/3.3 V).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06989-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs; requires different programming flow and ClockBuilder Pro v2.x	Targeted at space-constrained designs where crystal footprint must be eliminated; not drop-in compatible due to different pinout and register map	Select when ultra-low jitter and crystal integration are mandatory; expect layout and firmware changes
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or MultiSynth flexibility	Used in cost-sensitive, static-clock applications (e.g., legacy storage controllers); lacks frequency agility or spread-spectrum capability	Select only for simple, unchanging clock trees where programmability adds no value

Compared with SI5338C-B04168-GM, Si5332A-D06989-GM offers superior jitter and integration but demands redesign, while ICS853S01AGI-01LFT sacrifices programmability for lower BOM cost and simpler validation-making SI5338C-B04168-GM the optimal balance of flexibility, performance, and field-proven deployment.

Availability

SI5338C-B04168-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 platform development, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B04168-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-designed to replace multiple discrete oscillators with a single configurable IC.

FAQ

What is the maximum output frequency supported by SI5338C-B04168-GM?

The SI5338C-B04168-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as confirmed in Table 6 of the datasheet. This capability enables direct clocking of 10 GbE PHYs and PCIe Gen 4 SerDes without external frequency multipliers.

Does SI5338C-B04168-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B04168-GM is validated for PCIe Gen 4 Common Clock with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz), meeting PCI-SIG Base Specification 4.0 requirements. This is measured using 100 MHz HCSL outputs and verified with the Skyworks PCIe Clock Jitter Tool, as documented in Table 12 of the datasheet.

Can SI5338C-B04168-GM operate with a 25 MHz crystal input?

No-SI5338C-B04168-GM supports external crystals only in the 8–30 MHz range, and 25 MHz falls within that range. However, crystal drive level must remain ≤100 µW and load capacitance must be configured to match the on-chip 11–13 pF supported range (recommended 17–19 pF). Refer to Tables 8–11 for full crystal specifications.

How many independent supply voltages does SI5338C-B04168-GM support for its output drivers?

SI5338C-B04168-GM supports four independent output buffer supplies (VDDO0–VDDO3), each configurable to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage devices-for example, 1.8 V FPGA I/O banks, 2.5 V ASIC cores, and 3.3 V legacy peripherals-without external level shifters.

Is ClockBuilder Pro software required to configure SI5338C-B04168-GM?

While SI5338C-B04168-GM can be programmed directly via I²C using custom firmware, ClockBuilder Pro is strongly recommended for initial configuration, validation, and jitter optimization. It auto-generates register maps, validates MultiSynth settings, and exports .c files for embedded initialization-reducing bring-up time from days to hours.

SI5338C-B04168-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04168-GM FAQ

1.How can I place an order for SI5338C-B04168-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04168-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04168-GM reliable?

The price and inventory of SI5338C-B04168-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04168-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B04168-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04168-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04168-GM?

SI5338C-B04168-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04168-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04168-GM?

For technical support, including SI5338C-B04168-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04168-GM requirements.

6.How does Aetrix verify that SI5338C-B04168-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04168-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04168-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B04168-GM?

All SI5338C-B04168-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04168-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04168-GM part is unused and in its original packaging.

Return procedure for SI5338C-B04168-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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