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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04168-GMR

Name: SI5338C-B04168-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04168-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04168-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04168-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04168-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ), PCIe Gen 1–4 compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing applications.

For engineers reviewing the SI5338C-B04168-GMR datasheet, SI5338C-B04168-GMR pinout, SI5338C-B04168-GMR application, or SI5338C-B04168-GMR equivalent, key selection criteria include its 24-QFN package, 4× differential output capability, independent per-output voltage control (1.5–3.3 V), zero-ppm synthesis accuracy, and PCIe Gen 4 Common Clock jitter compliance (0.15–0.45 ps RMS).

Technical Context

The SI5338C-B04168-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (1.6 MHz loop bandwidth) locks to an external reference (crystal, CMOS, or differential input), followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output stage supports programmable phase offset (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and configurable spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).

Input flexibility includes eight clock sources: dual differential inputs (IN1/IN2, IN5/IN6; 5–710 MHz), two single-ended CMOS inputs (IN3/IN4; 5–200 MHz), and four additional inputs (IN3–IN6) supporting SSTL/HSTL (5–350 MHz). Output drivers are fully independent-each configurable for format, voltage (1.5/1.8/2.5/3.3 V), termination, and enable control via OEB pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Frequency range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock spec (0.15–0.45 ps RMS)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5–3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card use
Control interface	I²C/SMBus-compatible (up to 400 kHz); supports ClockBuilder Pro configuration and OTP NVM storage

Pinout & Package

SI5338C-B04168-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is top-left (marked dot), and the package is RoHS-compliant and halogen-free.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each supports LVPECL/LVDS/HCSL/CML with programmable swing and common-mode voltage
VDDO0 – VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing
SCL, SDA	I²C serial interface	Standard bidirectional bus (400 kHz max); used for register programming and status readback
INTR	Interrupt output	Open-drain signal indicating loss-of-lock, loss-of-signal, or other fault conditions
VDD	Core supply	Single 1.8/2.5/3.3 V supply powering PLL, synthesizers, and logic; PSRR > 60 dB
GND, RSVD_GND	Ground connections	Multiple dedicated GND pins and reserved ground pad ensure low-impedance return paths and EMI suppression

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true any-frequency generation (0.16–710 MHz) with 0 ppm error on all outputs
PCIe Gen 4 compliance	Meets Common Clock jitter requirements (0.15–0.45 ps RMS) without external filtering or reclocking
Glitchless frequency tuning	Hardware-supported frequency increment/decrement (1 ppm steps) with <667 ns update time and no output interruption
Programmable phase alignment	Independent phase offset per output (–45 to +45 ns range) with <20 ps step resolution for precise skew management
Flexible spread spectrum	Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, selectable center/down-spread mode

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed PCIe Gen 4 switch IC requiring synchronized, low-jitter reference clocks for upstream/downstream ports and management controller. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with PCIe Gen 4 Common Clock compliance and deterministic jitter <10 ps pk-pk. Use Value: Eliminates need for multiple discrete oscillators; reduces board area by 60% and ensures Gen 4 link training success without jitter margin derating.	Use Scenario: 10 GbE/25 GbE Ethernet switch ASIC needing scalable, multi-format clock distribution across SERDES lanes, CPU interface, and packet buffer subsystems. IC Role / Device Role / Timing Role: Quad-output timing hub delivering 156.25 MHz LVDS (SERDES), 250 MHz HCSL (PHY), 125 MHz CMOS (management), and 312.5 MHz LVPECL (buffer memory) simultaneously. Use Value: Enables single-chip clock solution for heterogeneous interface requirements; avoids inter-clock skew and simplifies layout with localized VDDO decoupling.
FPGA-Based Video Processing	Telecom Line Card Sync
Use Scenario: Broadcast video processing FPGA (e.g., Xilinx Versal) requiring pixel-accurate clocking for HDMI 2.1 TX/RX, DDR4 memory, and PCIe Gen 3 host interface. IC Role / Device Role / Timing Role: Configurable clock source generating 594 MHz LVDS (HDMI TMDS), 1200 MHz LVDS (DDR4 DQS), 100 MHz HCSL (PCIe), and 27 MHz CMOS (audio codec) with sub-20 ps inter-output skew. Use Value: Guarantees frame-synchronous operation across domains; eliminates video tearing and audio sync drift via hardware-aligned phase offsets.	Use Scenario: Carrier-grade telecom line card needing IEEE 1588 PTP grandmaster timing, SyncE EEC Option 2 compliance, and redundant reference switching. IC Role / Device Role / Timing Role: Dual-reference clock generator accepting Stratum 3 OC-12 (155.52 MHz) and GPS-disciplined 10 MHz, then synthesizing 2.048 MHz E1, 1.544 MHz T1, 10 MHz PTP, and 125 MHz SyncE with <0.7 ps RMS jitter. Use Value: Meets ITU-T G.8262 ePRTC holdover stability; enables seamless failover between primary/backup references without phase discontinuity.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed PCIe Gen 4 switch IC requiring synchronized, low-jitter reference clocks for upstream/downstream ports and management controller.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with PCIe Gen 4 Common Clock compliance and deterministic jitter <10 ps pk-pk.

Use Value: Eliminates need for multiple discrete oscillators; reduces board area by 60% and ensures Gen 4 link training success without jitter margin derating.

Use Scenario: 10 GbE/25 GbE Ethernet switch ASIC needing scalable, multi-format clock distribution across SERDES lanes, CPU interface, and packet buffer subsystems.

IC Role / Device Role / Timing Role: Quad-output timing hub delivering 156.25 MHz LVDS (SERDES), 250 MHz HCSL (PHY), 125 MHz CMOS (management), and 312.5 MHz LVPECL (buffer memory) simultaneously.

Use Value: Enables single-chip clock solution for heterogeneous interface requirements; avoids inter-clock skew and simplifies layout with localized VDDO decoupling.

FPGA-Based Video Processing

Telecom Line Card Sync

Use Scenario: Broadcast video processing FPGA (e.g., Xilinx Versal) requiring pixel-accurate clocking for HDMI 2.1 TX/RX, DDR4 memory, and PCIe Gen 3 host interface.

IC Role / Device Role / Timing Role: Configurable clock source generating 594 MHz LVDS (HDMI TMDS), 1200 MHz LVDS (DDR4 DQS), 100 MHz HCSL (PCIe), and 27 MHz CMOS (audio codec) with sub-20 ps inter-output skew.

Use Value: Guarantees frame-synchronous operation across domains; eliminates video tearing and audio sync drift via hardware-aligned phase offsets.

Use Scenario: Carrier-grade telecom line card needing IEEE 1588 PTP grandmaster timing, SyncE EEC Option 2 compliance, and redundant reference switching.

IC Role / Device Role / Timing Role: Dual-reference clock generator accepting Stratum 3 OC-12 (155.52 MHz) and GPS-disciplined 10 MHz, then synthesizing 2.048 MHz E1, 1.544 MHz T1, 10 MHz PTP, and 125 MHz SyncE with <0.7 ps RMS jitter.

Use Value: Meets ITU-T G.8262 ePRTC holdover stability; enables seamless failover between primary/backup references without phase discontinuity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower phase noise (0.35 ps RMS), but larger 32-QFN package and higher power (65 mA typ)	Better suited for ultra-low-jitter SerDes applications (e.g., 400G ZR coherent optics) where jitter budget is <0.4 ps RMS	Select when system requires >4 outputs or sub-0.4 ps RMS jitter; not drop-in due to pin count, footprint, and register map differences
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; 3.3 V only; no I²C interface or spread spectrum	Limited to static clock trees (e.g., legacy PCIe Gen 2 systems) where frequency agility and voltage flexibility are unnecessary	Choose for cost-sensitive, high-volume designs with unchanging clock plans; requires redesign for any frequency or format change

Compared with Si5332A-D06189-GM and ICS8430I-01T, the SI5338C-B04168-GMR delivers optimal balance of programmability, jitter performance, and compact 24-QFN packaging-making it ideal for space-constrained, multi-standard platforms like edge AI accelerators and 5G small cells where field-upgradable timing is essential.

Availability

SI5338C-B04168-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/routing, and FPGA-based video processing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B04168-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of clock IC innovation.

The Si5338 family was designed specifically for high-density, multi-protocol timing in datacenter, telecom, and broadcast systems-enabling consolidation of discrete oscillators into a single programmable, low-jitter, software-configurable clock generator.

FAQ

What is the maximum output frequency supported by SI5338C-B04168-GMR in LVPECL mode?

The SI5338C-B04168-GMR supports LVPECL outputs up to 710 MHz. This is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL, LVDS, and CML formats. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper termination with 100 Ω differential load and AC coupling for CML.

Does SI5338C-B04168-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B04168-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical 0.11 ps), as specified in Table 12 under "PCIe Gen 3 Separate Reference No Spread, SRNS" and extended to Gen 4 per Skyworks' application note AN562. Configuration requires setting PLL bandwidth to 2–4 MHz and CDR frequency to 10 MHz.

Can SI5338C-B04168-GMR generate different output voltages on each of its four output banks?

Yes, SI5338C-B04168-GMR supports independent output supply voltages per bank: VDDO0, VDDO1, VDDO2, and VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O, 2.5 V PHY, 3.3 V microcontroller) without level shifters.

Is ClockBuilder Pro software required to configure SI5338C-B04168-GMR?

No, ClockBuilder Pro is optional but strongly recommended. SI5338C-B04168-GMR can be configured via raw I²C register writes using any compatible controller. However, ClockBuilder Pro automates complex MultiSynth™ calculations, validates jitter performance, generates configuration files, and supports OTP programming-reducing bring-up time from days to minutes.

What is the thermal resistance (θJA) of SI5338C-B04168-GMR in still air?

The junction-to-ambient thermal resistance (θJA) of SI5338C-B04168-GMR is 37 °C/W under still-air conditions, as specified in Table 4 ("Thermal Characteristics"). This value assumes standard PCB layout with 2 oz copper, 4 thermal vias under the exposed pad, and minimal copper pour-critical for maintaining TJ < 125 °C at full 45 mA core current.

SI5338C-B04168-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04168-GMR FAQ

1.How can I place an order for SI5338C-B04168-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04168-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04168-GMR reliable?

The price and inventory of SI5338C-B04168-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04168-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B04168-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04168-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04168-GMR?

SI5338C-B04168-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04168-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04168-GMR?

For technical support, including SI5338C-B04168-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04168-GMR requirements.

6.How does Aetrix verify that SI5338C-B04168-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04168-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04168-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B04168-GMR?

All SI5338C-B04168-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04168-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04168-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B04168-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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