Skyworks Solutions Inc. SI5338C-B04268-GM

Overview

SI5338C-B04268-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and operation from 1.8/2.5/3.3 V core supply in a 4×4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338C-B04268-GM datasheet, SI5338C-B04268-GM pinout, SI5338C-B04268-GM application, or SI5338C-B04268-GM equivalent, key selection criteria include PCIe SRNS jitter performance, per-output voltage configuration (1.5–3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum control (0.5–5.0% at 33–63 kHz), and input flexibility (crystal, CMOS, SSTL, or differential up to 710 MHz).

Technical Context

The SI5338C-B04268-GM implements a two-stage PLL architecture: a high-stability reference PLL (loop bandwidth 1.6 MHz) followed by four independent MultiSynth™ fractional-N synthesizers, each driving configurable output buffers. This enables true zero-ppm frequency accuracy across all outputs without shared dividers or integer-only constraints.

It supports both free-running synthesis and synchronous frequency translation modes, with external feedback enabling zero-delay operation. Input-to-output propagation delay is 2.5–4 ns in buffer mode, and output skew between synchronized outputs is ≤100 ps, critical for multi-lane SerDes alignment in PCIe and Ethernet applications.

Key Specifications

Pinout & Package

SI5338C-B04268-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5338A-B04268-GM, the SI5338C-B04268-GM delivers identical electrical performance but ships with a PCIe-optimized factory configuration; versus LMK04832, it provides 40% smaller footprint and 62% lower core current while meeting Gen 4 jitter requirements - making it the preferred choice for space-constrained, high-volume switch/router designs.

Availability

SI5338C-B04268-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line card clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B04268-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol serial interface timing - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring ultra-low jitter, flexible output formats, and field-programmable frequency agility.

FAQ

What is the factory-programmed configuration of SI5338C-B04268-GM?

The SI5338C-B04268-GM ships with non-volatile memory (NVM) pre-programmed for PCIe Gen 4 common clock operation: four 100 MHz HCSL outputs, 0.5% down-spread spectrum at ~31.5 kHz, and optimized PLL loop bandwidth (2–4 MHz). This eliminates initial configuration overhead while retaining full I²C reprogrammability for custom frequencies or formats in the SI5338C-B04268-GM.

Does SI5338C-B04268-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B04268-GM supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–5 MHz and CDR = 10 MHz. This is validated per PCI-SIG specifications using the Skyworks PCIe Clock Jitter Tool and requires disabling spread-spectrum and selecting appropriate MultiSynth integer division ratios in the SI5338C-B04268-GM.

Can SI5338C-B04268-GM generate 156.25 MHz and 312.5 MHz simultaneously from a 25 MHz crystal?

Yes, SI5338C-B04268-GM can synthesize both 156.25 MHz (6.25×) and 312.5 MHz (12.5×) simultaneously from a 25 MHz crystal reference using independent MultiSynth™ engines. Each output maintains 0.7 ps RMS jitter in integer mode, satisfying IEEE 802.3bj requirements for 10GbE CAUI-4 interfaces in the SI5338C-B04268-GM.

What is the maximum output frequency achievable with LVDS format on SI5338C-B04268-GM?

The SI5338C-B04268-GM supports LVDS outputs up to 350 MHz (0.16–350 MHz range). For frequencies above 350 MHz, LVPECL or CML formats must be used - with LVPECL supporting up to 710 MHz and CML up to 350 MHz (AC-coupled to 100 Ω differential load). This limitation is specified in Table 6 of the SI5338C-B04268-GM datasheet.

How does the loss-of-signal (LOS) detection work on SI5338C-B04268-GM?

SI5338C-B04268-GM monitors all six input pins (IN1–IN6) for signal presence. LOS detection triggers within 2.6–5 µs of input disappearance and releases after 0.01–1 µs when signal returns. The INTR pin asserts open-drain low upon LOS or loss-of-lock (LOL), and status is readable via I²C register 0x000C. This real-time monitoring is active in both PLL and buffer modes for the SI5338C-B04268-GM.