Skyworks Solutions Inc. SI5338C-B04323-GM
- Part No.:
- SI5338C-B04323-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B04323-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B04323-GM from Skyworks Solutions is an I²C-programmable quad clock generator with MultiSynth™ technology, synthesizing four independent output clocks at any frequency (0.16–710 MHz) with 0 ppm precision. It supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs, operates from 1.8/2.5/3.3 V core supply, and delivers 0.7 ps RMS typical phase jitter-ideal for PCIe Gen 4, 10GbE, and FPGA clocking.
For engineers reviewing the SI5338C-B04323-GM datasheet, SI5338C-B04323-GM pinout, SI5338C-B04323-GM application, or SI5338C-B04323-GM equivalent, key selection considerations include differential input support up to 710 MHz, independent per-output voltage control (1.5–3.3 V), PCIe Gen 4 SRNS compliance, spread-spectrum capability (0.5–5.0% at 33–63 kHz), and I²C/SMBus programmability with ClockBuilder Pro software integration.
Technical Context
The SI5338C-B04323-GM implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six configurable inputs (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2. Each output driver is fully decoupled-supporting integer or fractional synthesis, independent phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps.
It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and highly configurable spread spectrum on any output (5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation). The device uses on-chip OTP NVM for configuration storage and supports both I²C register access and pin-controlled real-time adjustments (PINC/FDEC/OEB).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | Four differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS |
| Frequency range | 0.16–710 MHz per output; supports two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 Common Clock and Gen 3 SRNS requirements |
| Input flexibility | 6 inputs: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply & power | Single 1.8/2.5/3.3 V core supply; 45 mA typical core current; independent VDDOx per output (1.4–3.63 V) |
| Operating temp | –40 °C to +85 °C ambient, qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338C-B04323-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept AC-coupled differential reference (5–710 MHz); require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential clock outputs | Four independent pairs; each configurable for format, voltage, and slew rate |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output group-enables mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise timing performance |
| SCL, SDA | I²C interface | SMBus-compatible serial bus (up to 400 kHz); supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs without external crystals |
| PCIe Gen 4 compliance | Meets Common Clock and SRNS jitter specs (0.15–0.45 ps RMS) with 2–5 MHz PLL bandwidth and CDR = 10 MHz |
| Per-output voltage control | Each VDDOx rail independently set to 1.5/1.8/2.5/3.3 V-supports heterogeneous SoC/FPGA interfaces on single chip |
| Real-time frequency tuning | Glitchless ±1 ppm step adjustment via PINC/FDEC pins-enables dynamic clock scaling in live systems |
| Programmable phase offset | ±45 ns fine-grained skew control per output (20 ps resolution)-critical for SerDes alignment and DDR timing margin |
| Spread spectrum support | Configurable SSC on any output: 5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation-reduces EMI in dense PCB layouts |
Applications
| PCIe Gen 4 Switch Fabric | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz reference clocks across multiple SerDes lanes with sub-0.5 ps RMS jitter. IC Role / Device Role / Timing Role: Primary clock generator delivering four identical PCIe Gen 4 Common Clock outputs with matched skew and SRNS-compliant jitter. Use Value: Eliminates need for four discrete oscillators; enables single-point jitter optimization and simplified board layout with deterministic inter-lane skew <100 ps. | Use Scenario: 10GbE optical line card needing 156.25 MHz and 312.5 MHz clocks for PHY and MAC layers, plus auxiliary 25 MHz for management MCU. IC Role / Device Role / Timing Role: Quad-output frequency translator generating precise Ethernet-compliant clocks from a single 25 MHz crystal reference. Use Value: Reduces BOM count and footprint vs. discrete clock ICs; supports flexible PHY/MAC clock domain isolation via independent output voltage and format control. |
| FPGA-Based Broadcast Video Router | Telecom MSAN with Multi-Standard Sync |
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring 74.25 MHz, 148.5 MHz, and 297 MHz clocks with tight phase alignment. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating three harmonically related video clocks from one low-jitter reference. Use Value: Achieves <20 ps inter-output phase step resolution-ensures pixel-accurate frame synchronization across parallel video pipelines. | Use Scenario: Multi-service access node supporting TDM, Ethernet, and PON interfaces, each demanding distinct sync frequencies (e.g., 8 kHz, 155.52 MHz, 125 MHz). IC Role / Device Role / Timing Role: Universal timing hub accepting GPS-disciplined 10 MHz reference and generating protocol-specific clocks with holdover stability. Use Value: Replaces multiple dedicated clock ICs; provides loss-of-signal detection and alarm signaling for network sync monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06189-GM | Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter, supports JESD204B deterministic latency | Targeted at high-end data converters and radar systems requiring ultra-low jitter and deterministic delay | Select when >4 outputs, sub-0.4 ps jitter, or JESD204B timing control are required; not drop-in due to different pinout and register map |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; 3.3 V only; no spread spectrum | Cost-sensitive, static-clock applications like legacy telecom line cards with fixed 125/156.25 MHz requirements | Select for simple, unprogrammable clock fanout where frequency agility and multi-voltage support are unnecessary |
Compared with Si5332A-D06189-GM, SI5338C-B04323-GM offers broader input flexibility and simpler configuration but higher jitter; versus ICS8430I-01T, it provides full programmability and mixed-signal compatibility at the cost of higher design complexity.
Availability
SI5338C-B04323-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, and FPGA-based broadcast video routers requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338C-B04323-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.
The Si5338 product line was designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems-emphasizing jitter performance, configurability, and integration density over fixed-function alternatives.
FAQ
What is the maximum differential input frequency supported by the SI5338C-B04323-GM?
The SI5338C-B04323-GM supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed SerDes reference clocks without external division, preserving signal integrity and minimizing additive jitter in PCIe Gen 4 and 10GbE applications. The device requires external 100 Ω termination and maintains optimal jitter performance when input slew rates exceed 0.3 V/ns.
Does the SI5338C-B04323-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, the SI5338C-B04323-GM meets PCIe Gen 4 SRNS jitter specifications (0.11–0.32 ps RMS) when configured with a PLL bandwidth of 2–5 MHz and CDR = 10 MHz. Its MultiSynth™ architecture ensures deterministic phase relationships between outputs, and its low 0.7 ps RMS typical phase jitter provides margin against Gen 4 compliance limits. Configuration is validated using Skyworks' PCIe Clock Jitter Tool.
Can the SI5338C-B04323-GM generate four different output frequencies simultaneously?
Yes, the SI5338C-B04323-GM synthesizes four independent output frequencies simultaneously using its four MultiSynth™ engines. Each output (CLK0–CLK3) can be set to any frequency from 0.16 MHz to 710 MHz-including combinations like 100 MHz (PCIe), 156.25 MHz (Ethernet), 297 MHz (12G-SDI), and 25 MHz (MCU)-with zero ppm error and independent format/voltage control.
What is the purpose of the INTR pin on the SI5338C-B04323-GM?
The INTR pin on the SI5338C-B04323-GM is an open-drain interrupt output that signals loss-of-lock (LOL) or loss-of-signal (LOS) conditions detected by the internal PLL and input monitors. It allows host systems to implement real-time clock health monitoring and failover without polling I²C registers-critical for telecom and industrial applications requiring high system availability.
How does the SI5338C-B04323-GM handle power supply noise rejection?
The SI5338C-B04323-GM features excellent PSRR on its 1.8/2.5/3.3 V core supply (VDD), minimizing sensitivity to switching noise from adjacent DC-DC converters. Its architecture isolates the PLL's VCO and synthesis stages from supply ripple, ensuring the 0.7 ps RMS phase jitter specification holds across the full operating range (–40 °C to +85 °C) without requiring ultra-low-noise LDOs.
SI5338C-B04323-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B04323-GM FAQ
1.How can I place an order for SI5338C-B04323-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B04323-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B04323-GM reliable?
The price and inventory of SI5338C-B04323-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04323-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B04323-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04323-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B04323-GM?
SI5338C-B04323-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B04323-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B04323-GM?
For technical support, including SI5338C-B04323-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04323-GM requirements.
6.How does Aetrix verify that SI5338C-B04323-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B04323-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04323-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B04323-GM?
All SI5338C-B04323-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04323-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B04323-GM part is unused and in its original packaging.
Return procedure for SI5338C-B04323-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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