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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04443-GM

Name: SI5338C-B04443-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04443-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04443-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04443-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04443-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338C-B04443-GM datasheet, SI5338C-B04443-GM pinout, SI5338C-B04443-GM application, or SI5338C-B04443-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B04443-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving one output channel. Its synthesis resolution is 1 ppb, enabling true zero-ppm frequency accuracy on all outputs.

It supports flexible input references - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and provides independent phase adjustment (<20 ps step), frequency increment/decrement (1 ppm steps), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation rate) per output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common clock jitter requirements (≤0.45 ps RMS) under specified test conditions
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and processor clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables direct replacement of multiple XO sources without redesign
Output Voltage per Driver	1.5 / 1.8 / 2.5 / 3.3 V - allows mixed-voltage system interfacing (e.g., 1.8 V FPGA core + 3.3 V legacy peripheral)
Supply Voltage	Core: 1.8 / 2.5 / 3.3 V ±10%; Output buffers: 1.4–3.63 V - supports low-power 1.8 V systems and industrial 3.3 V rails
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating
Package	24-pin QFN, 4 × 4 mm - space-constrained PCBs requiring high-density timing solutions

Pinout & Package

SI5338C-B04443-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz LVDS/LVPECL/CML references; require external 100 Ω termination
IN3/IN4	Single-ended CMOS inputs	Support 5–200 MHz clock or crystal; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with per-driver VDDO supply
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output pair - enable mixed-signal voltage domain interfacing
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status flag for loss-of-lock and loss-of-signal alarms

Key Features

Feature	Design Value
Any-frequency synthesis on four outputs	Each output independently generates frequencies from 0.16 to 710 MHz with 1 ppb resolution - eliminates need for multiple XOs or discrete PLLs
PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance	Validated jitter performance (≤0.32 ps RMS for SRNS, ≤0.45 ps RMS for Gen 4 CC) - enables drop-in use in server and storage platforms
Independent per-output voltage and format	Four VDDO supplies (1.5/1.8/2.5/3.3 V) and selectable LVPECL/LVDS/HCSL/CMOS/SSTL - interfaces directly with heterogeneous SoC/FPGA peripherals
Glitchless frequency tuning	1 ppm-step increment/decrement via pin or I²C - enables real-time clock margining and dynamic frequency scaling without output interruption
Programmable spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI in dense PCB layouts without affecting timing margins

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complexes in a 1U rack server. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (≤0.45 ps RMS) HCSL clocks with matched skew (<100 ps) and independent SSC control per lane group. Use Value: Meets PCIe Gen 4 common clock jitter spec while eliminating four discrete oscillators and reducing BOM count and layout area by >60%.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three precise Ethernet frequencies from a single 25 MHz crystal reference, with independent output formats (LVDS for PHYs, CMOS for control logic). Use Value: Enables single-crystal timing architecture, simplifies clock tree design, and avoids inter-channel jitter coupling seen in daisy-chained buffers.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clock (74.25 MHz), reference clock (27 MHz), and DDR memory clock (400 MHz) to an FPGA-based video encoder with SMPTE 2110 compliance. IC Role / Device Role / Timing Role: Programmable quad clock generator with sub-20 ps phase step resolution, supporting precise inter-output phase alignment for multi-channel video sampling. Use Value: Eliminates external delay lines and manual trimming; achieves <±1 ns inter-clock skew required for SMPTE ST 2110-10 synchronization.	Use Scenario: Delivering 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to multiple framers and DSPs on a carrier-grade line card. IC Role / Device Role / Timing Role: High-stability clock translator accepting 19.44 MHz reference and synthesizing OC-n rates with 0.7 ps RMS jitter (OC-12 compliant). Use Value: Replaces legacy PLL+VCXO solutions with integrated, factory-trimmed jitter performance - reduces calibration time and field failure risk.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complexes in a 1U rack server.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (≤0.45 ps RMS) HCSL clocks with matched skew (<100 ps) and independent SSC control per lane group.

Use Value: Meets PCIe Gen 4 common clock jitter spec while eliminating four discrete oscillators and reducing BOM count and layout area by >60%.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in a Layer 3 switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three precise Ethernet frequencies from a single 25 MHz crystal reference, with independent output formats (LVDS for PHYs, CMOS for control logic).

Use Value: Enables single-crystal timing architecture, simplifies clock tree design, and avoids inter-channel jitter coupling seen in daisy-chained buffers.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clock (74.25 MHz), reference clock (27 MHz), and DDR memory clock (400 MHz) to an FPGA-based video encoder with SMPTE 2110 compliance.

IC Role / Device Role / Timing Role: Programmable quad clock generator with sub-20 ps phase step resolution, supporting precise inter-output phase alignment for multi-channel video sampling.

Use Value: Eliminates external delay lines and manual trimming; achieves <±1 ns inter-clock skew required for SMPTE ST 2110-10 synchronization.

Use Scenario: Delivering 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to multiple framers and DSPs on a carrier-grade line card.

IC Role / Device Role / Timing Role: High-stability clock translator accepting 19.44 MHz reference and synthesizing OC-n rates with 0.7 ps RMS jitter (OC-12 compliant).

Use Value: Replaces legacy PLL+VCXO solutions with integrated, factory-trimmed jitter performance - reduces calibration time and field failure risk.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and register map; lacks PCIe Gen 4 common clock validation and SRNS compliance testing	Not qualified for PCIe Gen 4 server backplanes requiring SRNS mode; suitable for Gen 3 and earlier	Select when PCIe Gen 4 SRNS is not required and cost optimization is prioritized
ICS8430I-01LG	Fixed-frequency, non-programmable quad LVDS output; no I²C interface or MultiSynth capability	Limited to pre-defined frequency combinations; cannot synthesize arbitrary frequencies like SI5338C-B04443-GM	Select only for static clock trees where all four outputs are fixed and known at design stage

Compared with Si5338A-B-GM, SI5338C-B04443-GM adds PCIe Gen 4 SRNS validation and tighter jitter characterization; compared with ICS8430I-01LG, it offers full I²C programmability and any-frequency synthesis - making it suitable for evolving, multi-standard platforms requiring field-upgradable timing.

Availability

SI5338C-B04443-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server backplanes, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B04443-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 product line delivers high-performance, software-programmable clock generation for datacenter, networking, and communications infrastructure - designed to replace multiple discrete oscillators while meeting stringent jitter and reliability requirements.

FAQ

What is the maximum output frequency supported by SI5338C-B04443-GM?

The SI5338C-B04443-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. Two outputs may simultaneously operate above 350 MHz (Fvco/4 and Fvco/6), but higher frequencies require integer-mode synthesis and proper VCO configuration. All values are confirmed in the official Skyworks datasheet Rev. 1.6, Table 6.

Does SI5338C-B04443-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B04443-GM is explicitly validated for PCIe Gen 3 SRNS and Gen 4 Common Clock compliance, with measured RMS jitter of ≤0.32 ps (Gen 3 SRNS) and ≤0.45 ps (Gen 4 CC) under specified test conditions (PLL BW 2–5 MHz, CDR = 10 MHz). This validation is documented in Table 12 of the Skyworks Si5338 datasheet Rev. 1.6.

Can SI5338C-B04443-GM generate different output voltages on each channel?

Yes, SI5338C-B04443-GM provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - verified in Table 3 (DC Characteristics) and Section 3.4 (Output Stage) of the datasheet.

Is ClockBuilder Pro software required to configure SI5338C-B04443-GM?

No, ClockBuilder Pro is optional but strongly recommended. SI5338C-B04443-GM supports standard I²C/SMBus programming (100/400 kHz) using custom firmware. However, ClockBuilder Pro automates register configuration, jitter optimization, and PCIe/ETH compliance checks - significantly reducing bring-up time versus manual register writes.

What is the thermal resistance (θJA) of SI5338C-B04443-GM in its 4 × 4 mm QFN package?

The SI5338C-B04443-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions, as specified in Table 4 (Thermal Characteristics) of the Skyworks datasheet Rev. 1.6. This value assumes standard PCB layout with thermal vias under the exposed pad - critical for maintaining <150 °C junction temperature at 45 mA core current.

SI5338C-B04443-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04443-GM FAQ

1.How can I place an order for SI5338C-B04443-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04443-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04443-GM reliable?

The price and inventory of SI5338C-B04443-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04443-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B04443-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04443-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04443-GM?

SI5338C-B04443-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04443-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04443-GM?

For technical support, including SI5338C-B04443-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04443-GM requirements.

6.How does Aetrix verify that SI5338C-B04443-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04443-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04443-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B04443-GM?

All SI5338C-B04443-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04443-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04443-GM part is unused and in its original packaging.

Return procedure for SI5338C-B04443-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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