Skyworks Solutions Inc. SI5338C-B04461-GMR
- Part No.:
- SI5338C-B04461-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B04461-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B04461-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338C-B04461-GMR datasheet, SI5338C-B04461-GMR pinout, SI5338C-B04461-GMR application, or SI5338C-B04461-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro software support.
Technical Context
The SI5338C-B04461-GMR implements a two-stage PLL architecture: a high-stability input stage with configurable reference inputs (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks driving each output. Each synthesis path supports integer or fractional mode operation with <20 ps phase step resolution and 1 ppm frequency increment/decrement capability.
Its output stage provides fully independent configuration per driver-including signal format, supply voltage (VDDOx), termination, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate)-enabling simultaneous generation of non-integer-related frequencies up to 710 MHz while maintaining PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3 |
| Operating Temperature | –40 °C to +85 °C ambient; qualified per industrial temperature grade requirements |
| Power Consumption | 45 mA typical core current at 100 MHz on all outputs with 25 MHz reference |
Pinout & Package
SI5338C-B04461-GMR uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports standard reflow profiles per JEDEC J-STD-020 and includes integrated ground plane for low-noise clock distribution.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs up to 350 MHz; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs (4 channels) | Each pair configurable as LVPECL/LVDS/HCSL/CML; independent VDDOx supply per channel |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V per output bank; decoupling required per datasheet layout guidelines |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for low power-supply-induced jitter |
| SCL, SDA | I²C interface | Standard SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal alarms |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Four independent MultiSynth™ engines enable zero-ppm precision generation of arbitrary frequencies without external crystals |
| PCIe Gen 4 compliance | Meets PCIe Base Spec 4.0 common clock jitter requirement (≤0.45 ps RMS) with 2–5 MHz PLL bandwidth |
| Independent output voltage control | Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling mixed-voltage system clocking |
| Glitchless frequency tuning | Hardware-supported ±1 ppm frequency increment/decrement via PINC/FDEC pins with sub-ns update latency |
| Programmable spread spectrum | Per-output SSC with adjustable spread (0.5–5.0%), rate (33–63 kHz), and direction-reducing EMI in dense PCB layouts |
Applications
| Ethernet Switch/Routing | PCIe Gen 1–4 Interconnect |
|---|---|
Use Scenario: High-density 10 GbE/25 GbE line cards requiring multiple synchronized clocks for MAC, PHY, and packet processor subsystems. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz, 312.5 MHz, 625 MHz, and 125 MHz outputs with sub-ps jitter for SerDes lane alignment. Use Value: Eliminates four discrete oscillators and reduces board area by >60% while meeting IEEE 802.3bj jitter budgets. | Use Scenario: Server motherboard with CPU, GPU, NVMe SSD, and add-in card slots-all requiring compliant PCIe reference clocks. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe Gen 3/4 reference to multiple endpoints with SRNS compliance. Use Value: Enables single-source timing architecture with guaranteed 0.11–0.32 ps RMS jitter in SRNS mode, simplifying validation. |
| Broadcast Video/Audio Timing | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/2110 IP video routers needing precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight skew control. IC Role / Device Role / Timing Role: Low-jitter clock synthesizer generating three independent video clocks plus a 10 MHz house sync reference. Use Value: Achieves <100 ps output-to-output skew and <0.7 ps RMS jitter-critical for artifact-free 4K/8K video transport. | Use Scenario: Heterogeneous compute platform with ARM SoC, Xilinx Zynq MPSoC, and DDR4 memory subsystems requiring distinct clock domains. IC Role / Device Role / Timing Role: Configurable clock hub delivering 500 MHz processor core clock, 200 MHz DDR4 interface clock, and 100 MHz peripheral bus clock. Use Value: Supports dynamic voltage/frequency scaling (DVFS) via I²C-controlled frequency stepping without glitching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05889-GM | Higher integration: 8 outputs, dual-loop architecture, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at high-speed data converters and radar systems requiring sub-100 fs jitter and deterministic delay | Choose Si5332A-D05889-GM when >4 outputs or JESD204B deterministic latency is required; not pin-compatible |
| ICS8430I-01T | Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum | Cost-sensitive applications where only standard frequencies (e.g., 100/125/156.25 MHz) are needed | Choose ICS8430I-01T for fixed-frequency, low-cost clock fanout; lacks any-frequency synthesis and configurability |
Compared with Si5332A-D05889-GM and ICS8430I-01T, SI5338C-B04461-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact 4×4 mm footprint-making it optimal for mid-tier networking and embedded computing where design reuse and rapid frequency iteration matter.
Availability
SI5338C-B04461-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 interconnect, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338C-B04461-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in space-constrained systems-enabling replacement of multiple discrete oscillators with a single programmable IC supporting PCIe, Ethernet, Fibre Channel, and broadcast video timing standards.
FAQ
What is the maximum output frequency supported by SI5338C-B04461-GMR in LVPECL mode?
The SI5338C-B04461-GMR supports up to 710 MHz in LVPECL output mode, as specified in Table 6 of the datasheet. This applies when using differential outputs with appropriate termination and layout practices to maintain signal integrity and jitter performance below 1 ps RMS.
Does SI5338C-B04461-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338C-B04461-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), verified per PCI Express Base Specification 4.0 rev. 0.5 using a 2–5 MHz PLL bandwidth and 10 MHz CDR. Configuration requires specific register settings via I²C or ClockBuilder Pro.
Can SI5338C-B04461-GMR generate four completely unrelated output frequencies simultaneously?
Yes, SI5338C-B04461-GMR uses four independent MultiSynth™ synthesis blocks, enabling truly unrelated frequencies (e.g., 100.123 MHz, 156.456 MHz, 212.789 MHz, 375.001 MHz) with zero ppm accuracy on each output-no shared dividers or constraints between channels.
What is the recommended programming tool for configuring SI5338C-B04461-GMR?
The recommended programming tool is Skyworks' ClockBuilder Pro software, a free GUI-based utility that enables full register configuration, jitter simulation, and .c file generation for embedded initialization. It supports SI5338C-B04461-GMR out-of-the-box and integrates with standard I²C host controllers.
Is SI5338C-B04461-GMR pin-compatible with other Si5338 variants like SI5338A or SI5338B?
Yes, all Si5338 variants-including SI5338C-B04461-GMR-are pin-compatible and share identical 24-pin QFN packaging, pin assignments, and power sequencing requirements. Functional differences (e.g., frequency range, jitter specs) are implemented in firmware and configuration registers, not hardware layout.
SI5338C-B04461-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B04461-GMR FAQ
1.How can I place an order for SI5338C-B04461-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B04461-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B04461-GMR reliable?
The price and inventory of SI5338C-B04461-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04461-GMR is usually 5 days.
3.What payment methods are accepted for SI5338C-B04461-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04461-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B04461-GMR?
SI5338C-B04461-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B04461-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B04461-GMR?
For technical support, including SI5338C-B04461-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04461-GMR requirements.
6.How does Aetrix verify that SI5338C-B04461-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338C-B04461-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04461-GMR meets industry standards.
7.What is the process for return or replacement of SI5338C-B04461-GMR?
All SI5338C-B04461-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04461-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B04461-GMR part is unused and in its original packaging.
Return procedure for SI5338C-B04461-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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