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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04503-GMR

Name: SI5338C-B04503-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04503-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04503-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04503-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04503-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs in a 4×4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338C-B04503-GMR datasheet, SI5338C-B04503-GMR pinout, SI5338C-B04503-GMR application, or SI5338C-B04503-GMR equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), PCIe Gen 4 common-clock compliance, independent per-output voltage control (1.5–3.3 V), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B04503-GMR integrates a high-stability PLL-based synthesis stage followed by four independent MultiSynth™ fractional-N dividers, enabling true zero-ppm frequency accuracy on all outputs. Its architecture supports both free-running synthesis and synchronous frequency translation modes using up to six input references (differential, CMOS, SSTL/HSTL).

Each output driver features independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), voltage control (1.5/1.8/2.5/3.3 V), and fine-grained phase adjustment (<20 ps steps). The device includes loss-of-lock and loss-of-signal alarms, spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and glitchless frequency increment/decrement at 1 ppm steps.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential outputs (CLK0A/B through CLK3A/B); supports up to eight single-ended or mixed configurations
Frequency range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 common-clock and SRNS requirements
Input reference support	Differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal
Supply & power	1.8/2.5/3.3 V core; 1.4–3.63 V per output bank; 45 mA typical core current at 100 MHz on all outputs
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B04503-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed across the Si5338 family per Skyworks documentation (Rev. 1.6, p. 37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled differential references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output banks; each pair (e.g., CLK0A/CLK0B) provides complementary signals
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V supply with >60 dB PSRR; powers PLL, logic, and memory
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation on all four outputs with 0 ppm precision-no external crystals required
PCIe Gen 4 compliance	Meets common-clock total jitter (≤33.6 ps pk-pk) and SRNS RMS jitter (≤0.45 ps) specs without external filtering
Per-output voltage control	Each of four output banks accepts independent VDDO (1.5/1.8/2.5/3.3 V), simplifying multi-voltage SoC/FPGA clock tree design
Glitchless frequency tuning	1 ppm step size with <667 ns update time enables real-time clock rate adaptation in test and calibration systems
Programmable phase offset	±45 ns range in <20 ps increments allows precise skew alignment between high-speed SerDes lanes
Spread-spectrum control	Configurable 0.5–5.0% down-spread at 33–63 kHz per output reduces EMI in dense PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (0.45 ps RMS) common-clock signals compliant with PCIe Gen 4 SRNS spec. Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all outputs under varying load conditions.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors on a carrier-grade router line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three distinct frequencies simultaneously with independent format (LVDS/HCSL) and voltage (1.8 V/2.5 V) control. Use Value: Reduces BOM count and layout area versus discrete clock solutions while supporting IEEE 802.3bj jitter requirements.
FPGA & ASIC Clocking	Broadcast Video Timing
Use Scenario: Supplying 200 MHz system clock, 400 MHz transceiver reference, and 50 MHz debug clock to a Xilinx Versal ACAP with mixed-voltage I/O banks. IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8 V/2.5 V/3.3 V) and format (LVDS/CMOS) selection. Use Value: Enables single-device clock tree for heterogeneous FPGA interfaces without level shifters or external buffers.	Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and ancillary timing signals (148.5 MHz, 74.25 MHz) to broadcast video encoder/decoder ASICs. IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) generator supporting 27 GHz-derived frequencies via integer/fractional synthesis. Use Value: Meets SMPTE ST 2082 jitter mask requirements for uncompressed 4K/8K video transport over coaxial or optical links.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (0.45 ps RMS) common-clock signals compliant with PCIe Gen 4 SRNS spec.

Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all outputs under varying load conditions.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors on a carrier-grade router line card.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three distinct frequencies simultaneously with independent format (LVDS/HCSL) and voltage (1.8 V/2.5 V) control.

Use Value: Reduces BOM count and layout area versus discrete clock solutions while supporting IEEE 802.3bj jitter requirements.

FPGA & ASIC Clocking

Broadcast Video Timing

Use Scenario: Supplying 200 MHz system clock, 400 MHz transceiver reference, and 50 MHz debug clock to a Xilinx Versal ACAP with mixed-voltage I/O banks.

IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8 V/2.5 V/3.3 V) and format (LVDS/CMOS) selection.

Use Value: Enables single-device clock tree for heterogeneous FPGA interfaces without level shifters or external buffers.

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock and ancillary timing signals (148.5 MHz, 74.25 MHz) to broadcast video encoder/decoder ASICs.

IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) generator supporting 27 GHz-derived frequencies via integer/fractional synthesis.

Use Value: Meets SMPTE ST 2082 jitter mask requirements for uncompressed 4K/8K video transport over coaxial or optical links.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06509-GM	Higher integration: 6 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for best performance	Targeted at ultra-low-jitter applications (e.g., 400G ZR coherent optics) where SI5338C-B04503-GMR's 0.7 ps RMS is insufficient	Select when sub-0.4 ps RMS jitter and >4 outputs are required; higher cost and larger 5×5 mm package
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 0.8 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjust	Suitable only for static clock trees where frequency changes are unnecessary post-manufacture	Choose for cost-sensitive, non-reconfigurable designs where programmability is not needed

Compared with Si5332A-D06509-GM and ICS8430I-01T, SI5338C-B04503-GMR uniquely balances full I²C programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact 4×4 mm footprint-making it optimal for field-upgradable, multi-protocol timing in space-constrained networking and compute platforms.

Availability

SI5338C-B04503-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet routing, FPGA clocking, and broadcast video applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B04503-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems-enabling consolidation of discrete oscillators and buffers into a single, PCIe- and Ethernet-compliant timing IC.

FAQ

What is the maximum output frequency supported by SI5338C-B04503-GMR?

The SI5338C-B04503-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per Skyworks Rev. 1.6 specification.

Does SI5338C-B04503-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B04503-GMR meets PCIe Gen 4 SRNS requirements with ≤0.32 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–4 MHz and CDR = 10 MHz, as verified in Table 12 of the Skyworks datasheet Rev. 1.6.

Can SI5338C-B04503-GMR generate different output voltages on each channel?

Yes, SI5338C-B04503-GMR provides four independent VDDO pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (1.8 V), HCSL (2.5 V), and CMOS (3.3 V) outputs without external level shifters.

What is the minimum input reference frequency for SI5338C-B04503-GMR in PLL bypass mode?

In PLL bypass (clock buffer) mode, SI5338C-B04503-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6), though loss-of-signal detection is disabled below 5 MHz per Skyworks Rev. 1.6, p. 8.

How is SI5338C-B04503-GMR programmed, and is ClockBuilder Pro required?

SI5338C-B04503-GMR is programmed via I²C/SMBus interface. While ClockBuilder Pro (free from Skyworks) simplifies configuration and validation, register-level programming is fully documented in the datasheet (Sections 5–6) and supported by custom firmware.

SI5338C-B04503-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04503-GMR FAQ

1.How can I place an order for SI5338C-B04503-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04503-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04503-GMR reliable?

The price and inventory of SI5338C-B04503-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04503-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B04503-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04503-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04503-GMR?

SI5338C-B04503-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04503-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04503-GMR?

For technical support, including SI5338C-B04503-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04503-GMR requirements.

6.How does Aetrix verify that SI5338C-B04503-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04503-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04503-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B04503-GMR?

All SI5338C-B04503-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04503-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04503-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B04503-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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