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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04726-GMR

Name: SI5338C-B04726-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04726-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04726-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04726-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B04726-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338C-B04726-GMR datasheet, SI5338C-B04726-GMR pinout, SI5338C-B04726-GMR application, or SI5338C-B04726-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz.

Technical Context

The SI5338C-B04726-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input supports eight clock sources - including 8–30 MHz crystals, 5–200 MHz CMOS, and 5–710 MHz differential references - enabling flexible system-level clock tree design.

Each output supports independent frequency, format, voltage, phase offset (<20 ps step resolution), spread-spectrum modulation (0.5–5.0% down-spread), and enable control. The device operates from a single 1.8/2.5/3.3 V core supply and features loss-of-lock and loss-of-signal alarms, I²C/SMBus interface, and glitchless frequency increment/decrement in 1 ppm steps.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements at 100 MHz HCSL output
Output Count & Type	4 differential outputs (CLK0A/B–CLK3A/B) - supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS formats
Frequency Range	0.16–710 MHz - covers PCIe (100/125 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and processor clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables direct replacement of multiple XO sources
Supply Voltage	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board designs with independent output rail control
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating
Package	24-pin QFN, 4 × 4 mm - surface-mount compatible with standard reflow profiles and 0.5 mm pitch

Pinout & Package

The SI5338C-B04726-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is located at top-left (IN1), and pins are numbered counter-clockwise. The package supports standard JEDEC reflow and provides low thermal resistance (θ_JA = 37 °C/W).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML references up to 710 MHz; internal 100 Ω termination enabled
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair configurable for LVPECL/LVDS/HCSL/CML with programmable VDDOx
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output bank - enables mixed-signal voltage domain interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, synthesizers, and control logic; PSRR optimized
SCL, SDA	I²C/SMBus interface	Standard 100 kHz/400 kHz operation; supports multi-device addressing on shared bus
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true 0 ppm frequency accuracy on all outputs without trimming
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode satisfies PCIe Base Spec 3.0 for endpoint timing
Glitchless frequency tuning	1 ppm step size with <667 ns update time via PINC/FDEC pins - enables real-time dynamic frequency scaling
Programmable phase offset	±45 ns range with <20 ps step resolution - supports precise skew alignment across multi-lane SerDes interfaces
Spread spectrum modulation	Configurable 0.5–5.0% down-spread at 33–63 kHz - reduces EMI peak emissions in dense PCB layouts
External feedback mode	Enables zero-delay buffer operation using external clock path - eliminates PLL-induced latency in synchronous systems

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in a server motherboard with multiple PCIe 4.0 x16 slots. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched propagation delay and phase alignment. Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk requirement while eliminating four discrete XOs and reducing board area by >60%.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric ASICs in a modular enterprise switch. IC Role / Device Role / Timing Role: Frequency translator and fanout buffer supporting mixed-rate Ethernet interfaces with independent voltage and format control per port. Use Value: Enables single-chip timing for multi-rate switching with <0.7 ps RMS jitter - avoids inter-port skew and meets IEEE 802.3bj jitter budgets.
FPGA-Based Video Processing	Telecom Line Card Sync
Use Scenario: Supplying pixel clocks (74.25 MHz), reference clocks (148.5 MHz), and DDR memory clocks (400 MHz) to a broadcast-grade video encoder FPGA. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating integer-related frequencies with sub-20 ps inter-output skew. Use Value: Eliminates need for multiple crystal oscillators and discrete fanout buffers while maintaining SMPTE ST 2082-1 timing integrity.	Use Scenario: Distributing Stratum 3-compliant 2.048 MHz and 19.44 MHz clocks across DS1/E1, T1/E1, and SONET OC-3/12 line interfaces in a carrier-grade access node. IC Role / Device Role / Timing Role: Low-phase-noise clock generator with OC-12 compliant jitter (<1 ps RMS) and loss-of-signal monitoring. Use Value: Achieves <0.7 ps RMS random jitter at 155.52 MHz - exceeds Telcordia GR-1244-CORE requirements for network element timing.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in a server motherboard with multiple PCIe 4.0 x16 slots.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched propagation delay and phase alignment.

Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk requirement while eliminating four discrete XOs and reducing board area by >60%.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric ASICs in a modular enterprise switch.

IC Role / Device Role / Timing Role: Frequency translator and fanout buffer supporting mixed-rate Ethernet interfaces with independent voltage and format control per port.

Use Value: Enables single-chip timing for multi-rate switching with <0.7 ps RMS jitter - avoids inter-port skew and meets IEEE 802.3bj jitter budgets.

FPGA-Based Video Processing

Telecom Line Card Sync

Use Scenario: Supplying pixel clocks (74.25 MHz), reference clocks (148.5 MHz), and DDR memory clocks (400 MHz) to a broadcast-grade video encoder FPGA.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating integer-related frequencies with sub-20 ps inter-output skew.

Use Value: Eliminates need for multiple crystal oscillators and discrete fanout buffers while maintaining SMPTE ST 2082-1 timing integrity.

Use Scenario: Distributing Stratum 3-compliant 2.048 MHz and 19.44 MHz clocks across DS1/E1, T1/E1, and SONET OC-3/12 line interfaces in a carrier-grade access node.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator with OC-12 compliant jitter (<1 ps RMS) and loss-of-signal monitoring.

Use Value: Achieves <0.7 ps RMS random jitter at 155.52 MHz - exceeds Telcordia GR-1244-CORE requirements for network element timing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs	Targeted at space-constrained, ultra-low-jitter applications like AI accelerators and 400G optical modules	Choose when board space is critical and jitter budget is <0.4 ps RMS; requires no external crystal
ICS853S02IAGLF	Fixed-frequency, non-programmable; 2-output LVDS; 0.9 ps RMS jitter; 3.3 V only	Limited to dual-output, fixed-ratio fanout in legacy telecom and storage systems	Choose only for cost-sensitive, static clock distribution where programmability is unnecessary

Compared with Si5332A-D06889-GM and ICS853S02IAGLF, the SI5338C-B04726-GMR offers field-programmable flexibility across four outputs, wider voltage/format support, and proven PCIe Gen 4 compliance - making it optimal for evolving high-speed serial interface designs requiring post-silicon timing optimization.

Availability

SI5338C-B04726-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25/100 GbE switch designs, broadcast video processing systems, and telecom line cards requiring stable component supply and long-term lifecycle support.

Supply support for SI5338C-B04726-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces - designed specifically to replace multiple fixed-frequency oscillators in PCIe, Ethernet, Fibre Channel, and processor-based systems.

FAQ

What is the maximum output frequency supported by the SI5338C-B04726-GMR in LVPECL format?

The SI5338C-B04726-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the official Skyworks datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 100G Ethernet applications. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and proper layout with controlled impedance and AC coupling is required for signal integrity.

Does the SI5338C-B04726-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) timing?

Yes, the SI5338C-B04726-GMR is explicitly validated for PCIe Gen 3 SRNS and meets PCIe Gen 4 common clock jitter specifications. Its 0.11–0.32 ps RMS jitter in SRNS mode (PLL BW 2–5 MHz, CDR = 10 MHz) complies with PCI-SIG Base Specification 4.0 rev. 0.5. The device achieves this using its MultiSynth™ architecture with optimized loop bandwidth and low-noise VCO design.

Can the SI5338C-B04726-GMR generate four different output frequencies simultaneously?

Yes, the SI5338C-B04726-GMR uses four independent MultiSynth™ fractional-N synthesizers to generate four fully independent output frequencies - each configurable from 0.16 to 710 MHz depending on format. Frequencies can be unrelated (e.g., 100 MHz PCIe, 125 MHz Ethernet, 156.25 MHz CPRI, 400 MHz DDR) with 0 ppm precision and sub-20 ps inter-output skew.

What input reference options does the SI5338C-B04726-GMR support?

The SI5338C-B04726-GMR accepts eight input reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). All inputs support automatic detection and loss-of-signal monitoring. External crystal operation requires no load capacitors due to on-chip 12 pF tuning capacitance.

Is ClockBuilder Pro software required to configure the SI5338C-B04726-GMR?

No, ClockBuilder Pro is optional but strongly recommended for initial configuration and validation of the SI5338C-B04726-GMR. The device supports full I²C/SMBus register-level programming in-system; however, ClockBuilder Pro automates MultiSynth™ divider calculations, validates jitter performance, generates configuration files, and exports to EEPROM - significantly reducing bring-up time and risk of misconfiguration.

SI5338C-B04726-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04726-GMR FAQ

1.How can I place an order for SI5338C-B04726-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04726-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04726-GMR reliable?

The price and inventory of SI5338C-B04726-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04726-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B04726-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04726-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04726-GMR?

SI5338C-B04726-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04726-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04726-GMR?

For technical support, including SI5338C-B04726-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04726-GMR requirements.

6.How does Aetrix verify that SI5338C-B04726-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04726-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04726-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B04726-GMR?

All SI5338C-B04726-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04726-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04726-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B04726-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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