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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04858-GM

Name: SI5338C-B04858-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04858-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04858-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04858-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04858-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed networking and FPGA timing applications.

For engineers reviewing the SI5338C-B04858-GM datasheet, SI5338C-B04858-GM pinout, SI5338C-B04858-GM application, or SI5338C-B04858-GM equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.

Technical Context

The SI5338C-B04858-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to the input reference, followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm accuracy and glitchless frequency tuning via dedicated PDEC/FDEC pins.

Its output stage provides full format and voltage configurability per driver - including LVPECL (0.16–710 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), and SSTL/HSTL (0.16–350 MHz) - with programmable initial phase offset (±45 ns), spread-spectrum control (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarms. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Format Flexibility	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently selectable
Per-Output Supply Voltage	1.5 V, 1.8 V, 2.5 V, or 3.3 V - enables mixed-voltage system clocking without level shifters
Frequency Tuning Resolution	1 ppm steps via dedicated pins; update time ≤667 ns for outputs >18 MHz
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom line card environments

Pinout & Package

SI5338C-B04858-GM is housed in a 4 mm × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), three output supply rails (VDDO0–VDDO3), core supply (VDD), I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; internal 20 kΩ pull-up/pull-down configurable
CLK0A/B–CLK3A/B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with per-output VDDO
VDDO0–VDDO3	Output buffer supply rails	Enable independent voltage setting per output pair (1.5/1.8/2.5/3.3 V) for mixed-signal interfacing
SCL/SDA	I²C serial interface	SMBus-compatible; supports standard/fast-mode (100/400 kHz); used for configuration and status readback
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or other fault conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable any-frequency generation with 0 ppm error on all outputs
PCIe Gen 1–4 compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS), validated with Intel Clock Jitter Tool
Glitchless frequency tuning	Hardware-controlled PDEC/FDEC pins allow real-time 1 ppm step adjustments without output interruption
Programmable phase alignment	±45 ns initial offset and <20 ps step resolution per output for precise inter-channel skew control
Spread-spectrum clocking	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI

Applications

PCIe Gen 4 Switch Fabric	Ethernet 10GbE Line Card
Use Scenario: High-density switch ASIC requiring four synchronized, low-jitter clocks at 100 MHz (HCSL), 250 MHz (LVDS), 322.265625 MHz (LVPECL), and 156.25 MHz (LVDS) for SerDes lanes, MAC, PHY, and management subsystems. IC Role / Device Role / Timing Role: Quad clock generator providing independent, jitter-clean references with PCIe Gen 4 SRNS compliance and per-output voltage control. Use Value: Eliminates four discrete oscillators and external level shifters; reduces board area by >60% and meets Intel's 0.32 ps RMS jitter limit for SRNS mode.	Use Scenario: 10GbE optical line card with dual XAUI interfaces, host processor, and packet buffer memory, needing 156.25 MHz (LVDS), 125 MHz (LVDS), 100 MHz (HCSL), and 25 MHz (CMOS) clocks. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal I/O (LVDS/HCSL/CMOS) and flexible reference input (crystal or recovered clock). Use Value: Enables single-device timing for multi-protocol interfaces; simplifies BOM and eliminates inter-clock skew via programmable phase offsets.
Broadcast Video Timing	FPGA-Based Video Processing
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz (LVDS), 74.25 MHz (LVDS), 148.5 MHz (LVDS), and 297 MHz (LVDS) clocks with sub-100 ps inter-output skew. IC Role / Device Role / Timing Role: Precision timing IC delivering broadcast-grade jitter performance (<0.7 ps RMS) and deterministic phase relationships across all outputs. Use Value: Meets SMPTE RP 184 jitter limits; eliminates need for external jitter cleaners or delay-matched trace routing.	Use Scenario: High-end video processing FPGA (e.g., Xilinx Versal) requiring 500 MHz (LVPECL), 300 MHz (LVDS), 100 MHz (HCSL), and 25 MHz (CMOS) clocks for logic fabric, transceivers, DDR4 memory, and control peripherals. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output format/voltage control and hardware-based frequency tuning. Use Value: Supports dynamic reconfiguration of FPGA clock domains; enables real-time frame-rate adaptation via PDEC/FDEC pin control.

PCIe Gen 4 Switch Fabric

Ethernet 10GbE Line Card

Use Scenario: High-density switch ASIC requiring four synchronized, low-jitter clocks at 100 MHz (HCSL), 250 MHz (LVDS), 322.265625 MHz (LVPECL), and 156.25 MHz (LVDS) for SerDes lanes, MAC, PHY, and management subsystems.

IC Role / Device Role / Timing Role: Quad clock generator providing independent, jitter-clean references with PCIe Gen 4 SRNS compliance and per-output voltage control.

Use Value: Eliminates four discrete oscillators and external level shifters; reduces board area by >60% and meets Intel's 0.32 ps RMS jitter limit for SRNS mode.

Use Scenario: 10GbE optical line card with dual XAUI interfaces, host processor, and packet buffer memory, needing 156.25 MHz (LVDS), 125 MHz (LVDS), 100 MHz (HCSL), and 25 MHz (CMOS) clocks.

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal I/O (LVDS/HCSL/CMOS) and flexible reference input (crystal or recovered clock).

Use Value: Enables single-device timing for multi-protocol interfaces; simplifies BOM and eliminates inter-clock skew via programmable phase offsets.

Broadcast Video Timing

FPGA-Based Video Processing

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz (LVDS), 74.25 MHz (LVDS), 148.5 MHz (LVDS), and 297 MHz (LVDS) clocks with sub-100 ps inter-output skew.

IC Role / Device Role / Timing Role: Precision timing IC delivering broadcast-grade jitter performance (<0.7 ps RMS) and deterministic phase relationships across all outputs.

Use Value: Meets SMPTE RP 184 jitter limits; eliminates need for external jitter cleaners or delay-matched trace routing.

Use Scenario: High-end video processing FPGA (e.g., Xilinx Versal) requiring 500 MHz (LVPECL), 300 MHz (LVDS), 100 MHz (HCSL), and 25 MHz (CMOS) clocks for logic fabric, transceivers, DDR4 memory, and control peripherals.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output format/voltage control and hardware-based frequency tuning.

Use Value: Supports dynamic reconfiguration of FPGA clock domains; enables real-time frame-rate adaptation via PDEC/FDEC pin control.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and architecture; lacks factory-programmed configuration (B04858 includes preloaded firmware for specific frequency set)	Requires full ClockBuilder Pro configuration; not drop-in for preprogrammed use cases	Select when custom frequency sets or field reprogramming are required
LMK04832ISQE/NOPB	Two PLLs (not four independent MultiSynths); higher power (120 mA typ); larger 48-QFN package	Better suited for ultra-low-noise RF clocking; less flexible for arbitrary multi-frequency synthesis	Select when sub-0.1 ps RMS jitter or dual-loop clean-up is mandatory, not for cost/space-constrained PCIe switching

Compared with Si5338A-B-GM and LMK04832ISQE/NOPB, the SI5338C-B04858-GM delivers factory-optimized timing for PCIe Gen 4 and 10GbE systems in the smallest footprint (4×4 mm), with lower power (45 mA) and simpler I²C-based bring-up - making it ideal for high-volume, space-constrained networking and FPGA platforms where preconfigured reliability matters.

Availability

SI5338C-B04858-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and guaranteed preprogrammed functionality.

Supply support for SI5338C-B04858-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure and mobility markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in data center switches, telecom line cards, and FPGA-based systems - emphasizing low jitter, software-defined flexibility, and compact integration.

FAQ

What is the factory-programmed configuration of the SI5338C-B04858-GM?

The SI5338C-B04858-GM is preprogrammed with a specific frequency set optimized for PCIe Gen 4 common clock applications: 100 MHz (HCSL), 250 MHz (LVDS), 322.265625 MHz (LVPECL), and 156.25 MHz (LVDS). This eliminates the need for initial I²C programming during system boot, reducing firmware complexity and startup time. The configuration is stored in one-time-programmable (OTP) memory inside the SI5338C-B04858-GM and cannot be overwritten.

Does the SI5338C-B04858-GM support spread-spectrum clocking (SSC) on all outputs?

Yes, the SI5338C-B04858-GM supports independent spread-spectrum clocking on any output, with user-selectable spread percentage (0.5–5.0% down-spread) and modulation rate (33–63 kHz). This feature is implemented in the MultiSynth™ stage and does not require external components. SSC can be enabled or disabled per output via I²C register writes, and the SI5338C-B04858-GM retains its factory SSC settings unless explicitly modified.

What reference inputs are compatible with the SI5338C-B04858-GM?

The SI5338C-B04858-GM accepts multiple reference types: external 8–30 MHz crystals (differential), 5–200 MHz CMOS signals (on IN3/IN4), 5–350 MHz SSTL/HSTL inputs, or 5–710 MHz differential clocks (on IN1/IN2 or IN5/IN6). All inputs are internally terminated and support automatic loss-of-signal detection. The SI5338C-B04858-GM does not require external biasing or level-shifting circuitry for any supported input type.

How is phase alignment controlled across the four outputs of the SI5338C-B04858-GM?

The SI5338C-B04858-GM provides independent programmable phase offset on each output, with ±45 ns range and <20 ps step resolution. Phase is adjusted digitally in the MultiSynth™ output divider stage, enabling deterministic skew control without analog delay lines. These settings are stored in OTP memory for the SI5338C-B04858-GM and persist across power cycles, ensuring repeatable inter-output timing relationships critical for SerDes lane deskew.

Is the SI5338C-B04858-GM pin-compatible with other Si5338 variants?

Yes, the SI5338C-B04858-GM shares the identical 24-QFN package and pinout with all Si5338A/B/C/D variants, including Si5338A-B-GM and Si5338D-B-GM. All share the same VDD, VDDOx, CLKxA/B, INx, SCL/SDA, and INTR pin assignments. However, factory-programmed configurations (like that in SI5338C-B04858-GM) are unique to the B04858 variant and not replicated in other part numbers.

SI5338C-B04858-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04858-GM FAQ

1.How can I place an order for SI5338C-B04858-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04858-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04858-GM reliable?

The price and inventory of SI5338C-B04858-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04858-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B04858-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04858-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04858-GM?

SI5338C-B04858-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04858-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04858-GM?

For technical support, including SI5338C-B04858-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04858-GM requirements.

6.How does Aetrix verify that SI5338C-B04858-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04858-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04858-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B04858-GM?

All SI5338C-B04858-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04858-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04858-GM part is unused and in its original packaging.

Return procedure for SI5338C-B04858-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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