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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04858-GMR

Name: SI5338C-B04858-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04858-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04858-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04858-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04858-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS), 0 ppm synthesis accuracy, 0.7 ps RMS typical phase jitter, and supports PCIe Gen 1–4 common-clock and SRNS compliance in a 4 × 4 mm 24-QFN package for FPGA and processor timing applications.

For engineers reviewing the SI5338C-B04858-GMR datasheet, SI5338C-B04858-GMR pinout, SI5338C-B04858-GMR application, or SI5338C-B04858-GMR equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL), independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), loss-of-lock/loss-of-signal alarms, and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338C-B04858-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), 20 ps step resolution, and glitchless frequency increment/decrement in 1 ppm steps.

It features flexible input handling - including external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - and configurable output drivers supporting LVPECL (0.16–710 MHz), LVDS (0.16–350 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), and SSTL/HSTL (0.16–350 MHz), all with independent VDDO supply per driver.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent clock outputs (CLK0A/B through CLK3A/B)
Max Output Frequency	710 MHz (LVPECL/LVDS); limited to two >350 MHz frequencies simultaneously (Fvco/4 & Fvco/6)
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz, LVDS/HCSL/LVPECL/CML, 125 MHz output, 25 MHz ref)
Frequency Accuracy	True zero ppm synthesis precision across all outputs using MultiSynth™ technology
Supply Voltages	Core: 1.8 / 2.5 / 3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per VDDOx
Operating Temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports SMBus alert response

Pinout & Package

SI5338C-B04858-GMR is housed in a thermally enhanced 4 × 4 mm, 24-lead QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND), and pin 13 (INTR) provides interrupt signaling for loss-of-lock and loss-of-signal events.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four fully independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
VDDO0–VDDO3	Per-output buffer supplies	Enable independent voltage setting (1.5/1.8/2.5/3.3 V) for mixed-signal system level translation
SCL, SDA	I²C serial interface	Supports configuration, status readback, and real-time frequency/phase adjustment without reset
INTR	Open-drain interrupt output	Asserts low on loss-of-lock (LOL) or loss-of-signal (LOS); requires external pull-up resistor

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true any-frequency generation on all four outputs with zero ppm error and <20 ps phase step resolution
PCIe Gen 4 compliance	Meets PCIe Gen 4 common-clock jitter spec (0.15–0.45 ps RMS) with PLL BW 2–5 MHz and CDR = 10 MHz
Independent spread spectrum	Configurable SSC on any output: 5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation rate
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption
External feedback mode	Supports zero-delay operation by routing an output back to INx for deterministic latency alignment
Low-power core	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference; 12 mA in buffer-only mode

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed PCIe Gen 4 switch IC requiring synchronous 100 MHz differential clocks with strict jitter limits (≤0.45 ps RMS). IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, low-jitter HCSL outputs for SerDes lanes and management logic. Use Value: Meets PCIe Gen 4 SRNS jitter requirements without external jitter cleaners; eliminates need for multiple discrete oscillators.	Use Scenario: 10 GbE/25 GbE Ethernet switch ASIC needing multiple independent clocks (125 MHz, 156.25 MHz, 312.5 MHz) with tight skew control. IC Role / Device Role / Timing Role: Quad-output frequency translator generating precise Ethernet PHY and MAC clocks from a single 25 MHz crystal. Use Value: Reduces BOM count and board space vs. four separate XO/VCXOs; enables dynamic reconfiguration via I²C during link training.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-10 ps cycle-cycle jitter. IC Role / Device Role / Timing Role: Master timing source delivering three independent LVDS clocks with programmable phase offsets for pixel alignment. Use Value: Achieves broadcast-grade jitter performance (0.7 ps RMS) directly from silicon; avoids analog delay-line calibration.	Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring core logic, transceiver, and DDR4 memory clocks with independent voltage and format control. IC Role / Device Role / Timing Role: Configurable clock hub supplying LVDS (transceivers), HCSL (DDR4), and CMOS (logic) clocks from one device. Use Value: Enables mixed-voltage domain clocking (1.8 V DDR4, 2.5 V transceivers, 3.3 V I/O) without level shifters or additional regulators.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed PCIe Gen 4 switch IC requiring synchronous 100 MHz differential clocks with strict jitter limits (≤0.45 ps RMS).

IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, low-jitter HCSL outputs for SerDes lanes and management logic.

Use Value: Meets PCIe Gen 4 SRNS jitter requirements without external jitter cleaners; eliminates need for multiple discrete oscillators.

Use Scenario: 10 GbE/25 GbE Ethernet switch ASIC needing multiple independent clocks (125 MHz, 156.25 MHz, 312.5 MHz) with tight skew control.

IC Role / Device Role / Timing Role: Quad-output frequency translator generating precise Ethernet PHY and MAC clocks from a single 25 MHz crystal.

Use Value: Reduces BOM count and board space vs. four separate XO/VCXOs; enables dynamic reconfiguration via I²C during link training.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-10 ps cycle-cycle jitter.

IC Role / Device Role / Timing Role: Master timing source delivering three independent LVDS clocks with programmable phase offsets for pixel alignment.

Use Value: Achieves broadcast-grade jitter performance (0.7 ps RMS) directly from silicon; avoids analog delay-line calibration.

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform requiring core logic, transceiver, and DDR4 memory clocks with independent voltage and format control.

IC Role / Device Role / Timing Role: Configurable clock hub supplying LVDS (transceivers), HCSL (DDR4), and CMOS (logic) clocks from one device.

Use Value: Enables mixed-voltage domain clocking (1.8 V DDR4, 2.5 V transceivers, 3.3 V I/O) without level shifters or additional regulators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06983-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), but fixed 4-output LVDS-only; no HCSL/CMOS support	Best for compact, crystal-less designs where only LVDS outputs are needed and ultra-low jitter is critical	Select when eliminating external crystal and minimizing jitter outweigh flexibility in output format and voltage
ICS853S02IAGLF	Non-programmable, fixed-frequency 4-output LVDS clock fanout buffer; no synthesis, no I²C, no spread spectrum	Only suitable for static clock distribution where input frequency matches all required outputs exactly	Select only for cost-sensitive, unchanging clock trees with no frequency translation or dynamic adjustment needs

Compared with Si5332A-D06983-GM, SI5338C-B04858-GMR offers broader output format and voltage flexibility at slightly higher jitter; compared with ICS853S02IAGLF, it provides full programmability and synthesis capability essential for multi-standard systems.

Availability

SI5338C-B04858-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, broadcast video synchronization, and FPGA-based embedded computing requiring stable component supply and long-term design-in support.

Supply support for SI5338C-B04858-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in high-performance analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 family was designed specifically for high-density, multi-protocol systems requiring flexible, low-jitter clock synthesis - targeting PCIe, Ethernet, telecom, and broadcast video applications where replacing multiple oscillators with one programmable device reduces cost and complexity.

FAQ

What is the maximum differential input frequency supported by SI5338C-B04858-GMR?

The SI5338C-B04858-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed reference clocks such as 622.08 MHz OC-12 or 710 MHz SerDes references without external division. Input slew rate must exceed 0.3 V/ns for optimal jitter performance.

Does SI5338C-B04858-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B04858-GMR meets PCIe Gen 4 SRNS jitter requirements (0.11–0.32 ps RMS) when configured with PLL bandwidth of 2–4 MHz or 2–5 MHz and CDR = 10 MHz. This mode is validated per PCI-Express Base Specification 4.0 rev. 0.5 and confirmed in Skyworks' AN562 application note.

Can SI5338C-B04858-GMR generate both LVDS and HCSL outputs simultaneously?

Yes, SI5338C-B04858-GMR supports mixed output formats: for example, CLK0A/B as LVDS (100 MHz), CLK1A/B as HCSL (100 MHz), CLK2A/B as CMOS (50 MHz), and CLK3A/B as SSTL (156.25 MHz). Each output driver has independent format, voltage, and termination control via I²C register configuration.

What is the purpose of the INTR pin on SI5338C-B04858-GMR?

The INTR pin on SI5338C-B04858-GMR is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) conditions. It enables real-time system monitoring without polling, allowing host processors to trigger failover or diagnostics. An external pull-up resistor is required for proper operation.

How is SI5338C-B04858-GMR programmed, and is ClockBuilder Pro required?

SI5338C-B04858-GMR is programmed via its I²C/SMBus interface using standard read/write commands. While ClockBuilder Pro is recommended for GUI-based configuration and .c file generation, register-level programming is fully documented in the Si5338 Register Map (Rev. 1.6). All settings - including frequency, format, voltage, and SSC - are stored in on-chip OTP NVM.

SI5338C-B04858-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04858-GMR FAQ

1.How can I place an order for SI5338C-B04858-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04858-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04858-GMR reliable?

The price and inventory of SI5338C-B04858-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04858-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B04858-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04858-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04858-GMR?

SI5338C-B04858-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04858-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04858-GMR?

For technical support, including SI5338C-B04858-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04858-GMR requirements.

6.How does Aetrix verify that SI5338C-B04858-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04858-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04858-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B04858-GMR?

All SI5338C-B04858-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04858-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04858-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B04858-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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