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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04870-GM

Name: SI5338C-B04870-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04870-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04870-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04870-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04870-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338C-B04870-GM datasheet, SI5338C-B04870-GM pinout, SI5338C-B04870-GM application, or SI5338C-B04870-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz), independent output voltage per driver (1.5/1.8/2.5/3.3 V), low-power 45 mA core supply, and 24-QFN 4 × 4 mm package with I²C/SMBus configuration.

Technical Context

The SI5338C-B04870-GM implements a two-stage PLL architecture: a high-performance integer-N PLL for reference frequency multiplication, followed by four independent MultiSynth™ fractional-N synthesis blocks enabling glitchless frequency/phase adjustment on each output. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable drive strength and independent VDDO (1.5–3.3 V). Spread spectrum modulation (0.5–5.0% spread, 33–63 kHz rate) and loss-of-lock/loss-of-signal alarms are integrated for system-level timing integrity and EMI reduction.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements without external cleanup
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 212.5/266.7 MHz
Input Reference Support	8–30 MHz crystal, 5–710 MHz differential - enables direct replacement of legacy XO-based clock trees
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDO = 1.5/1.8/2.5/3.3 V - allows mixed-voltage system integration without level shifters
Package	24-QFN, 4 × 4 mm - space-constrained PCBs benefit from compact footprint and thermal resistance θJA = 37 °C/W
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) - compatible with most microcontroller and FPGA I/O banks

Pinout & Package

SI5338C-B04870-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential outputs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C bus), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz with independent VDDO0
CLK1A / CLK1B	Differential Output Pair 1	Independent frequency, format, and voltage vs. CLK0; enables multi-domain clocking (e.g., CPU + PCIe + Ethernet)
CLK2A / CLK2B	Differential Output Pair 2	Supports HCSL up to 250 MHz for PCIe Gen 3/4 root complex applications
CLK3A / CLK3B	Differential Output Pair 3	Programmable phase offset (<20 ps step) for skew-critical interfaces like DDR memory clocks
SCL / SDA	I²C Serial Interface	Allows full device configuration and real-time monitoring without dedicated programming hardware
INTR	Interrupt Output	Asserts on loss-of-lock or loss-of-signal events; enables firmware-triggered failover or diagnostics
VDDO0–VDDO3	Output Buffer Supplies	Per-output voltage control eliminates need for external level translators in mixed-voltage SoC/FPGA designs
IN1/IN2, IN5/IN6	Differential Reference Inputs	Accept 5–710 MHz AC-coupled signals; internal 10 kΩ termination simplifies interface design
IN3/IN4	Single-Ended Reference Inputs	Support CMOS/SSTL/HSTL; 0.7×VDD VIH threshold ensures robust noise margin at 200 MHz

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs each synthesize any frequency from 0.16 to 710 MHz with true zero ppm accuracy
PCIe Gen 1–4 Compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS); validated using Intel Clock Jitter Tool
Independent Output Voltage Control	VDDO0–VDDO3 support 1.5/1.8/2.5/3.3 V per driver - eliminates external level-shifting components
Glitchless Frequency Adjustment	1 ppm step size via PINC/FDEC pins or I²C - enables dynamic clock scaling without system reset
Programmable Phase Offset	±45 ns range with <20 ps resolution - critical for DDR timing alignment and SerDes deskew
Spread Spectrum Modulation	Configurable 0.5–5.0% down-spread at 33–63 kHz - reduces EMI peaks without affecting timing margins

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Root Complex
Use Scenario: Synchronizing 10 GbE MAC/PHY, packet buffer, and switch fabric across multi-lane interfaces. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks. Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining sub-1 ps RMS jitter on all outputs.	Use Scenario: Driving CPU, GPU, and peripheral PCIe slots with strict common-clock jitter limits. IC Role / Device Role / Timing Role: Generates 100 MHz PCIe reference clocks with SRNS-compliant jitter (0.11–0.32 ps RMS) and independent HCSL drive. Use Value: Enables single-chip timing solution for multi-slot motherboards, reducing BOM count and improving signal integrity over daisy-chained clocks.
Processor & FPGA Clocking	Broadcast Video/Audio Timing
Use Scenario: Supplying core, memory, and I/O clocks to heterogeneous SoCs or Xilinx/Intel FPGAs with mixed voltage domains. IC Role / Device Role / Timing Role: Delivers 500 MHz LVDS for FPGA transceivers, 200 MHz CMOS for DDR3/4 controllers, and 100 MHz LVPECL for processor cores - each with independent VDDO. Use Value: Removes need for multiple clock buffers and level translators, cutting board area and power by >30% vs. discrete solutions.	Use Scenario: Generating SMPTE ST 2082 (12G-SDI), AES3, and genlock reference clocks in broadcast encoders/switchers. IC Role / Device Role / Timing Role: Produces 297 MHz (12G-SDI), 48 kHz audio master, and 27 MHz video sync from a single 25 MHz crystal input. Use Value: Achieves <10 ps pk-pk period jitter required for uncompressed video transport, avoiding costly jitter cleaners.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Root Complex

Use Scenario: Synchronizing 10 GbE MAC/PHY, packet buffer, and switch fabric across multi-lane interfaces.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks.

Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining sub-1 ps RMS jitter on all outputs.

Use Scenario: Driving CPU, GPU, and peripheral PCIe slots with strict common-clock jitter limits.

IC Role / Device Role / Timing Role: Generates 100 MHz PCIe reference clocks with SRNS-compliant jitter (0.11–0.32 ps RMS) and independent HCSL drive.

Use Value: Enables single-chip timing solution for multi-slot motherboards, reducing BOM count and improving signal integrity over daisy-chained clocks.

Processor & FPGA Clocking

Broadcast Video/Audio Timing

Use Scenario: Supplying core, memory, and I/O clocks to heterogeneous SoCs or Xilinx/Intel FPGAs with mixed voltage domains.

IC Role / Device Role / Timing Role: Delivers 500 MHz LVDS for FPGA transceivers, 200 MHz CMOS for DDR3/4 controllers, and 100 MHz LVPECL for processor cores - each with independent VDDO.

Use Value: Removes need for multiple clock buffers and level translators, cutting board area and power by >30% vs. discrete solutions.

Use Scenario: Generating SMPTE ST 2082 (12G-SDI), AES3, and genlock reference clocks in broadcast encoders/switchers.

IC Role / Device Role / Timing Role: Produces 297 MHz (12G-SDI), 48 kHz audio master, and 27 MHz video sync from a single 25 MHz crystal input.

Use Value: Achieves <10 ps pk-pk period jitter required for uncompressed video transport, avoiding costly jitter cleaners.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same architecture but lacks PCIe Gen 4 Common Clock validation; lower max output frequency (550 MHz vs. 710 MHz)	Suitable for PCIe Gen 1–3 only; not certified for Gen 4 jitter compliance	Select when Gen 4 support is unnecessary and cost optimization is prioritized
ICS8430I-01LG	Fixed-frequency, non-programmable quad LVDS generator; no I²C interface or MultiSynth™ flexibility	Limited to pre-defined frequencies; requires external crystals per output	Choose only for static, low-complexity clock trees where reconfiguration is not required

Compared with Si5338A-B-GM and ICS8430I-01LG, SI5338C-B04870-GM uniquely delivers PCIe Gen 4 Common Clock compliance, 710 MHz maximum output, and full I²C programmability - making it the only option for future-proof, high-density timing in next-gen servers and AI accelerators.

Availability

SI5338C-B04870-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server platforms, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B04870-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast systems - emphasizing low jitter, multi-format flexibility, and seamless integration with modern SoCs and FPGAs.

FAQ

What is the maximum output frequency supported by the SI5338C-B04870-GM?

The SI5338C-B04870-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. This capability enables direct clocking of PCIe Gen 4 (100 MHz), 12G-SDI (297 MHz), and high-speed SerDes lanes without external frequency multipliers. The 710 MHz limit applies specifically to differential outputs under specified load conditions.

Does the SI5338C-B04870-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B04870-GM is validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz bandwidth), meeting PCI-SIG Base Specification 4.0 rev. 0.5. It achieves this using a 2–5 MHz PLL loop bandwidth and CDR = 10 MHz test conditions, and is verified with the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

How many independent output supply voltages does the SI5338C-B04870-GM support?

The SI5338C-B04870-GM supports four independent output supply pins - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous driving of mixed-voltage devices (e.g., 1.8 V FPGA I/O, 3.3 V MCU, 2.5 V PHY) without external level shifters, reducing component count and signal integrity risk.

Can the SI5338C-B04870-GM generate spread spectrum clocking (SSC)?

Yes, the SI5338C-B04870-GM supports fully programmable spread spectrum on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and frequency range 5–350 MHz. Default settings are ~0.5% down-spread at ~31.5 kHz. SSC is configured per-output via I²C registers and requires no external components, aiding EMI certification in dense PCB layouts.

What reference inputs are compatible with the SI5338C-B04870-GM?

The SI5338C-B04870-GM accepts eight reference input configurations: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). Input pins IN1/IN2 and IN5/IN6 support AC-coupled differential clocks with internal 10 kΩ termination; IN3/IN4 accept DC-coupled single-ended signals with 0.7×VDD VIH threshold.

SI5338C-B04870-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04870-GM FAQ

1.How can I place an order for SI5338C-B04870-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04870-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04870-GM reliable?

The price and inventory of SI5338C-B04870-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04870-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B04870-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04870-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04870-GM?

SI5338C-B04870-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04870-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04870-GM?

For technical support, including SI5338C-B04870-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04870-GM requirements.

6.How does Aetrix verify that SI5338C-B04870-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04870-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04870-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B04870-GM?

All SI5338C-B04870-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04870-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04870-GM part is unused and in its original packaging.

Return procedure for SI5338C-B04870-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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