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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B04993-GMR

Name: SI5338C-B04993-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B04993-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B04993-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B04993-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B04993-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338C-B04993-GMR datasheet, SI5338C-B04993-GMR pinout, SI5338C-B04993-GMR application, or SI5338C-B04993-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% deviation), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338C-B04993-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal, CMOS, SSTL/HSTL, or differential inputs from 5–710 MHz) feeds a fractional-N MultiSynth™ synthesis stage per output. Each of the four outputs supports independent frequency, format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage, phase offset (±45 ns), and spread-spectrum modulation.

It features loss-of-lock and loss-of-signal alarms, glitchless frequency increment/decrement in 1 ppm steps, and <20 ps phase step resolution. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and includes on-chip OTP NVM for factory or field programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 to +85 °C ambient; qualified per industrial-grade reliability standards
Programmability	I²C/SMBus interface; factory-programmed OTP memory; supported by ClockBuilder Pro GUI tool

Pinout & Package

SI5338C-B04993-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are standardized across the Si5338 family per Skyworks Rev. 1.6 datasheet (page 37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs (4 channels)	Each pair supports LVPECL/LVDS/HCSL/CML; independently configurable format, frequency, and VDDOx
VDDO0–VDDO3	Output buffer supply rails	Per-output voltage control (1.5/1.8/2.5/3.3 V); decoupling required per channel
VDD	Core supply	Single 1.8/2.5/3.3 V supply; PSRR optimized; 45 mA typical current draw at full load
SCL, SDA	I²C serial interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports SMBus alerts
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration errors

Key Features

Feature	Design Value
Any-frequency synthesis	Four independent outputs each programmable from 0.16 to 710 MHz with true zero-ppm accuracy via MultiSynth™
Flexible output configuration	Each output supports LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats with independent VDDOx (1.5–3.3 V)
Glitchless frequency tuning	1 ppm step size with pin- or I²C-controlled increment/decrement; update time ≤667 ns above 18 MHz
Precision phase control	±45 ns programmable initial phase offset and <20 ps phase step resolution per output
Spread-spectrum clocking	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, down-spread default
Robust monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal events with sub-10 ms detection latency

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: High-speed 10/25/100 GbE switch ASICs requiring low-jitter, multi-frequency reference clocks for SerDes lanes and management subsystems. IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, spread-spectrum-capable outputs: two 100 MHz HCSL for PCIe Gen 4 root complex, one 125 MHz LVDS for SGMII, one 25 MHz CMOS for management MCU. Use Value: Meets PCIe Gen 4 common clock TJ <33.6 ps pk-pk and 0.45 ps RMS jitter specs while enabling per-lane SSC to reduce EMI without layout changes.	Use Scenario: Carrier-grade Ethernet switches supporting 1 GbE, 10 GbE, and 25 GbE interfaces with mixed PHY timing requirements. IC Role / Device Role / Timing Role: Quad-output clock source delivering 125 MHz LVDS for 10GBase-R, 156.25 MHz LVPECL for CPRI/eCPRI, 25 MHz CMOS for control plane, and 100 MHz HCSL for packet processing SoCs. Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs to meet IEEE 802.3bj/802.3by jitter budgets and enables dynamic frequency scaling via I²C.
Broadcast Video Synchronization	FPGA-Based Video Processing
Use Scenario: SMPTE ST 2082/ST 2110 IP video routers requiring genlock-capable, ultra-low-jitter clocks for frame synchronization and transport stream timing. IC Role / Device Role / Timing Role: Master timing IC generating 27 MHz LVDS (SDI), 74.25 MHz LVPECL (HD-SDI), 148.5 MHz LVDS (3G-SDI), and 10 MHz CMOS (reference for PLLs). Use Value: Delivers <10 ps pk-pk period jitter and ±20 ps inter-output skew-critical for maintaining lip-sync and avoiding video buffer underruns in real-time transport.	Use Scenario: High-end FPGA-based video encoders/decoders needing multiple precise clocks for pixel processing, DDR memory, transceivers, and control logic. IC Role / Device Role / Timing Role: Configurable clock hub supplying 148.5 MHz LVDS (video pipeline), 300 MHz LVDS (DDR4 interface), 100 MHz HCSL (GT transceivers), and 50 MHz CMOS (ARM Cortex-A9 subsystem). Use Value: Enables single-device clock tree with independent voltage and format per domain; eliminates board-level clock fanout ICs and reduces BOM count by 4×.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: High-speed 10/25/100 GbE switch ASICs requiring low-jitter, multi-frequency reference clocks for SerDes lanes and management subsystems.

IC Role / Device Role / Timing Role: Primary clock generator providing four synchronized, spread-spectrum-capable outputs: two 100 MHz HCSL for PCIe Gen 4 root complex, one 125 MHz LVDS for SGMII, one 25 MHz CMOS for management MCU.

Use Value: Meets PCIe Gen 4 common clock TJ <33.6 ps pk-pk and 0.45 ps RMS jitter specs while enabling per-lane SSC to reduce EMI without layout changes.

Use Scenario: Carrier-grade Ethernet switches supporting 1 GbE, 10 GbE, and 25 GbE interfaces with mixed PHY timing requirements.

IC Role / Device Role / Timing Role: Quad-output clock source delivering 125 MHz LVDS for 10GBase-R, 156.25 MHz LVPECL for CPRI/eCPRI, 25 MHz CMOS for control plane, and 100 MHz HCSL for packet processing SoCs.

Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs to meet IEEE 802.3bj/802.3by jitter budgets and enables dynamic frequency scaling via I²C.

Broadcast Video Synchronization

FPGA-Based Video Processing

Use Scenario: SMPTE ST 2082/ST 2110 IP video routers requiring genlock-capable, ultra-low-jitter clocks for frame synchronization and transport stream timing.

IC Role / Device Role / Timing Role: Master timing IC generating 27 MHz LVDS (SDI), 74.25 MHz LVPECL (HD-SDI), 148.5 MHz LVDS (3G-SDI), and 10 MHz CMOS (reference for PLLs).

Use Value: Delivers <10 ps pk-pk period jitter and ±20 ps inter-output skew-critical for maintaining lip-sync and avoiding video buffer underruns in real-time transport.

Use Scenario: High-end FPGA-based video encoders/decoders needing multiple precise clocks for pixel processing, DDR memory, transceivers, and control logic.

IC Role / Device Role / Timing Role: Configurable clock hub supplying 148.5 MHz LVDS (video pipeline), 300 MHz LVDS (DDR4 interface), 100 MHz HCSL (GT transceivers), and 50 MHz CMOS (ARM Cortex-A9 subsystem).

Use Value: Enables single-device clock tree with independent voltage and format per domain; eliminates board-level clock fanout ICs and reduces BOM count by 4×.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05889-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-ASIC systems; requires more complex configuration	Choose for new designs needing >4 outputs, tighter jitter, or deterministic delay; not drop-in due to pinout and register map differences
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Used in cost-sensitive, static-clock applications like legacy telecom line cards where frequency agility is unnecessary	Choose only when frequencies are fixed and programmability is not required; lacks Si5338C-B04993-GMR's flexibility and PCIe compliance

Compared with Si5332A-D05889-GM and ICS8430I-01T, the SI5338C-B04993-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and industrial temperature operation in a compact 24-QFN footprint-making it optimal for mid-volume, multi-standard timing applications where design reuse and future-proofing matter.

Availability

SI5338C-B04993-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server backplanes, broadcast video infrastructure, and FPGA-based embedded vision systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B04993-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and precision timing expertise.

The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in data center, telecom, and broadcast equipment-emphasizing low jitter, flexible I²C programmability, and robust industrial operation.

FAQ

What is the primary function of the SI5338C-B04993-GMR?

The SI5338C-B04993-GMR is an I²C-programmable quad clock generator IC that synthesizes up to four independent, ultra-low-jitter output clocks (0.16–710 MHz) from a single reference input. It serves as a replacement for multiple crystal oscillators in systems requiring precise, flexible timing-such as PCIe Gen 4 switches, Ethernet routers, and broadcast video equipment-while supporting LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL output formats.

Does the SI5338C-B04993-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B04993-GMR meets PCIe Gen 4 common clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) and total jitter <33.6 ps pk-pk, as verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4. It is explicitly listed in the datasheet as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant, making it suitable for root complex and endpoint timing in Gen 4 server and storage platforms.

How is the SI5338C-B04993-GMR programmed and configured?

The SI5338C-B04993-GMR is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software, which provides GUI-based frequency planning, register configuration, and OTP programming. Configuration can be performed in-system or during manufacturing. The device includes on-chip OTP memory for storing factory- or user-defined settings, enabling standalone operation after power-up without host intervention.

What package type and thermal characteristics does the SI5338C-B04993-GMR have?

The SI5338C-B04993-GMR uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load within the –40 to +85 °C industrial temperature range. The package is RoHS-compliant and moisture sensitivity level 3, requiring standard reflow handling per JEDEC J-STD-020.

Can the SI5338C-B04993-GMR generate spread-spectrum clocking (SSC) on individual outputs?

Yes, the SI5338C-B04993-GMR supports independent spread-spectrum clocking on any output, with programmable parameters including spread magnitude (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread default). This capability is implemented per-output in hardware and does not require external components-enabling EMI reduction in sensitive applications like high-density server boards or broadcast equipment without affecting other clock domains.

SI5338C-B04993-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B04993-GMR FAQ

1.How can I place an order for SI5338C-B04993-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B04993-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B04993-GMR reliable?

The price and inventory of SI5338C-B04993-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B04993-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B04993-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B04993-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B04993-GMR?

SI5338C-B04993-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B04993-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B04993-GMR?

For technical support, including SI5338C-B04993-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B04993-GMR requirements.

6.How does Aetrix verify that SI5338C-B04993-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B04993-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B04993-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B04993-GMR?

All SI5338C-B04993-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B04993-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B04993-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B04993-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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