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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05004-GM

Name: SI5338C-B05004-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05004-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05004-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05004-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05004-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and FPGA-based compute platforms.

For engineers reviewing the SI5338C-B05004-GM datasheet, SI5338C-B05004-GM pinout, SI5338C-B05004-GM application, or SI5338C-B05004-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus programmability.

Technical Context

The SI5338C-B05004-GM implements a two-stage PLL architecture: a high-performance integer-N PLL for reference frequency multiplication (synthesis stage 1), followed by four independent MultiSynth™ fractional-N synthesizers (stage 2) enabling precise, zero-ppm frequency generation on each of CLK0A/B through CLK3A/B. Its input stage accepts differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal references.

Each output driver supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL formats with independent supply voltage selection (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and I²C register access enable robust system-level timing control.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements at 100 MHz HCSL output
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 212.5/425 MHz, and processor core clocks
Input Reference Support	8–30 MHz crystal, or 5–710 MHz differential/CMOS/SSTL/HSTL - enables flexible clock tree sourcing without external buffers
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows mixed-voltage system integration with FPGA I/O banks and SerDes receivers
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with high-density PCB layouts and automated assembly
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) - enables configuration via microcontroller or host CPU during boot or runtime

Pinout & Package

SI5338C-B05004-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is located at top-left (IN1), and pins are numbered counter-clockwise. The package supports reflow soldering per JEDEC J-STD-020 and provides low thermal resistance (θ_JA = 37 °C/W).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL references (5–350 MHz); VIL/VIH referenced to VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four independent outputs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDO supply
VDDO0 – VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-signal interface voltage matching
SCL, SDA	I²C serial interface	Standard bidirectional bus; supports SMBus timeout and alert response protocol
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or NVM programming completion
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, synthesizers, and control logic; PSRR > 60 dB
GND, RSVD_GND	Ground connections	Eight GND pins including dedicated analog/digital ground returns and thermal pad connection

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals or trimming
PCIe Gen 1–4 compliance	Meets total jitter (33.6 ps pk-pk Gen 2), RMS jitter (0.11–0.45 ps RMS Gen 3/4), and SRNS requirements without external filtering
Independent output voltage per driver	Permits direct interfacing to diverse receivers (e.g., 1.8 V FPGA I/O, 3.3 V legacy logic, 1.5 V DDR memory) without level shifters
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) reduces EMI peak emissions in dense PCB layouts
Glitchless frequency adjustment	1 ppm incremental tuning via PINC/FDEC pins or I²C - maintains continuous clock output during dynamic frequency scaling
External feedback mode	Supports zero-delay buffer operation using CLKOUT as feedback - eliminates propagation delay in synchronous clock distribution

Applications

PCIe Switch Timing	FPGA Processor Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and identical SSC profiles. Use Value: Eliminates four discrete oscillators while meeting PCIe SRNS jitter spec (≤0.32 ps RMS) and simplifying BOM management.	Use Scenario: Generating core, I/O, and transceiver clocks for Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators. IC Role / Device Role / Timing Role: Configurable clock source supplying 300 MHz core, 156.25 MHz GTY transceiver, and 100 MHz AXI interface clocks from one device. Use Value: Enables precise inter-clock phase alignment (±20 ps step) and independent voltage control (1.0 V core, 1.8 V I/O, 0.9 V transceiver) without external regulators.
Ethernet Line Card Sync	Broadcast Video Master Clock
Use Scenario: Delivering 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 10GbE PHYs, packet processors, and SerDes in telecom line cards. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating IEEE 1588 PTP-aligned clocks with deterministic phase offset for time-sensitive networking. Use Value: Achieves sub-100 ps output-to-output skew and supports external feedback for zero-delay loop-back timing in TSN-aware systems.	Use Scenario: Serving as master timing source for SMPTE ST 2110 IP video routers requiring 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with tight jitter budgets. IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) quad generator with independent HCSL/LVDS outputs driving multiple video processing ASICs. Use Value: Meets SMPTE ST 2059-2 Class A jitter limits (<1.5 ps RMS) across all outputs while supporting frame-accurate phase synchronization.

PCIe Switch Timing

FPGA Processor Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and identical SSC profiles.

Use Value: Eliminates four discrete oscillators while meeting PCIe SRNS jitter spec (≤0.32 ps RMS) and simplifying BOM management.

Use Scenario: Generating core, I/O, and transceiver clocks for Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators.

IC Role / Device Role / Timing Role: Configurable clock source supplying 300 MHz core, 156.25 MHz GTY transceiver, and 100 MHz AXI interface clocks from one device.

Use Value: Enables precise inter-clock phase alignment (±20 ps step) and independent voltage control (1.0 V core, 1.8 V I/O, 0.9 V transceiver) without external regulators.

Ethernet Line Card Sync

Broadcast Video Master Clock

Use Scenario: Delivering 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 10GbE PHYs, packet processors, and SerDes in telecom line cards.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating IEEE 1588 PTP-aligned clocks with deterministic phase offset for time-sensitive networking.

Use Value: Achieves sub-100 ps output-to-output skew and supports external feedback for zero-delay loop-back timing in TSN-aware systems.

Use Scenario: Serving as master timing source for SMPTE ST 2110 IP video routers requiring 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with tight jitter budgets.

IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) quad generator with independent HCSL/LVDS outputs driving multiple video processing ASICs.

Use Value: Meets SMPTE ST 2059-2 Class A jitter limits (<1.5 ps RMS) across all outputs while supporting frame-accurate phase synchronization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05089-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-channel RF systems where deterministic latency and ultra-low jitter are critical	Select when >4 outputs or sub-0.5 ps RMS jitter required; not drop-in due to different pinout and power architecture
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; higher jitter (1.2 ps RMS); 32-pin TQFP	Used in cost-sensitive, static-clock applications where frequency flexibility is unnecessary and layout space permits larger package	Select only for fixed 100/125 MHz distribution; lacks I²C configurability, spread spectrum, or voltage flexibility of SI5338C-B05004-GM

Compared with Si5332A-D05089-GM and ICS853S01AGI-01LFT, the SI5338C-B05004-GM delivers optimal balance of programmability, jitter performance, and package size for PCIe/FPGA timing - offering full I²C configurability in a 4×4 mm QFN without requiring external regulators or sacrificing phase noise.

Availability

SI5338C-B05004-GM is available at Aetrix Electronics and suitable for PCIe switch timing, FPGA processor clocking, Ethernet line card synchronization, and broadcast video master clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05004-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and precision timing expertise.

The Si5338 family was designed specifically for high-speed serial interface timing in datacenter, telecom, and computing systems - emphasizing low jitter, multi-format output flexibility, and field-programmability to replace discrete oscillator arrays.

FAQ

What is the maximum output frequency supported by SI5338C-B05004-GM?

The SI5338C-B05004-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the MultiSynth™ architecture. All outputs maintain 0.7 ps RMS jitter at 100 MHz HCSL, verified per PCIe Gen 4 specifications.

Does SI5338C-B05004-GM support spread-spectrum clocking (SSC)?

Yes, SI5338C-B05004-GM supports fully programmable spread-spectrum clocking on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and selectable center-spread or down-spread modes. Default configuration is 0.5% down-spread at ~31.5 kHz. SSC parameters are configured via I²C registers and do not require external components.

Can SI5338C-B05004-GM operate with a single-ended input clock?

Yes, SI5338C-B05004-GM accepts single-ended CMOS, SSTL, or HSTL inputs on pins IN3 and IN4, supporting frequencies from 5 to 350 MHz. Input thresholds are referenced to VDD (VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD), and slew rate >1 V/ns is recommended for optimal jitter performance. Differential inputs remain available on IN1/IN2 and IN5/IN6 for higher-noise immunity.

What is the power consumption of SI5338C-B05004-GM under typical operating conditions?

SI5338C-B05004-GM draws 45 mA typical core supply current (VDD) when all outputs run at 100 MHz with a 25 MHz reference clock. Output buffer current varies by format and frequency: e.g., 30 mA max for LVPECL at 710 MHz, 8 mA for LVDS at 710 MHz, and 6–18 mA for CMOS depending on load and VDDO. Total system current is sum of VDD and individual VDDOx supplies.

Is SI5338C-B05004-GM pin-compatible with other Si5338 variants?

Yes, all Si5338 variants-including SI5338C-B05004-GM-share identical 24-pin QFN packaging, pinout, and footprint. Differences reside in factory-programmed NVM content (e.g., default frequencies, output formats, SSC settings), not hardware. This enables drop-in replacement across Si5338 part numbers without PCB redesign.

SI5338C-B05004-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05004-GM FAQ

1.How can I place an order for SI5338C-B05004-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05004-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05004-GM reliable?

The price and inventory of SI5338C-B05004-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05004-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05004-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05004-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05004-GM?

SI5338C-B05004-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05004-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05004-GM?

For technical support, including SI5338C-B05004-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05004-GM requirements.

6.How does Aetrix verify that SI5338C-B05004-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05004-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05004-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05004-GM?

All SI5338C-B05004-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05004-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05004-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05004-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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