Skyworks Solutions Inc. SI5338C-B05004-GMR

Overview

SI5338C-B05004-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS-compliant timing, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338C-B05004-GMR datasheet, SI5338C-B05004-GMR pinout, SI5338C-B05004-GMR application, or SI5338C-B05004-GMR equivalent, this page delivers verified specifications including PCIe Gen 4 common-clock jitter (0.15–0.45 ps RMS), independent per-output voltage selection (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B05004-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider for reference conditioning, followed by four independent MultiSynth™ synthesis blocks each with M/N/P dividers enabling fractional-N synthesis. Each output driver supports format- and voltage-selectable termination with integrated 22 Ω series resistors.

It features loss-of-signal and loss-of-lock detection, independent 20 ps step phase adjustment per output, glitchless ±1 ppm frequency increment/decrement via pin or I²C control, and configurable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output - all operating across –40 to +85 °C with 1.8/2.5/3.3 V core supply.

Key Specifications

Pinout & Package

SI5338C-B05004-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family layout and validated for signal integrity in high-speed clock distribution.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338C-B05002-GM, SI5338C-B05004-GMR offers out-of-box PCIe Gen 4 readiness and simplified qualification; versus LMK04832ISQE/NOPB, it provides lower cost, smaller footprint, and adequate jitter for mainstream compute/communication platforms without JESD204B requirements.

Availability

SI5338C-B05004-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server boards, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05004-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-density, multi-protocol timing consolidation in networking, computing, and broadcast systems - enabling replacement of multiple XOs with a single programmable, low-jitter clock generator.

FAQ

What is the factory-programmed configuration of SI5338C-B05004-GMR?

The SI5338C-B05004-GMR is pre-programmed with a PCIe Gen 4 common-clock configuration, including optimized PLL bandwidth (2–5 MHz), spread-spectrum disabled by default, and output drivers set for 100 MHz HCSL. It ships with non-volatile memory (OTP) containing this profile, enabling immediate use without initial I²C programming - though full reconfiguration remains possible via ClockBuilder Pro or direct register writes.

Does SI5338C-B05004-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B05004-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This requires I²C reprogramming to disable spread spectrum, adjust loop filter settings, and configure output format/voltage - capabilities fully supported by the device's MultiSynth™ engine and documented in Skyworks AN562.

Can SI5338C-B05004-GMR generate four different frequencies simultaneously above 350 MHz?

No - SI5338C-B05004-GMR can output only two unique frequencies above 350 MHz simultaneously (Fvco/4 and Fvco/6), as constrained by its VCO architecture. For example, it may generate 473.33 MHz and 710 MHz concurrently, but not four distinct >350 MHz clocks. Frequencies ≤350 MHz have no such restriction and support full four-output independence.

What is the minimum input clock slew rate required for optimal jitter performance on SI5338C-B05004-GMR?

For optimal jitter, SI5338C-B05004-GMR requires ≥0.3 V/ns differential input slew rate on IN1/IN2/IN5/IN6 pins and ≥1.0 V/ns single-ended slew rate on IN3/IN4 pins. Failure to meet these thresholds increases deterministic jitter - particularly critical for PCIe Gen 4 and 10 GbE applications where sub-ps RMS performance is mandatory.

Is external termination required for differential outputs of SI5338C-B05004-GMR?

Yes - LVPECL and LVDS outputs require external 100 Ω differential termination at the receiver end. HCSL outputs require AC coupling into a 100 Ω differential load. The SI5338C-B05004-GMR integrates 22 Ω series resistors on all differential outputs; therefore, PCB traces should be impedance-controlled to 78 Ω (LVDS) or 85 Ω (LVPECL) to achieve proper 100 Ω net termination with the internal resistor.