Skyworks Solutions Inc. SI5338C-B05006-GM
- Part No.:
- SI5338C-B05006-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05006-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,202
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Product details
Overview
SI5338C-B05006-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply - used in FPGA clocking, PCIe switch timing, and broadcast video synchronization.
For engineers reviewing the SI5338C-B05006-GM datasheet, SI5338C-B05006-GM pinout, SI5338C-B05006-GM application, or SI5338C-B05006-GM equivalent, this page provides verified technical context, exact pin functions, real-world application cards, validated alternatives, and supply support for industrial and high-speed serial interface designs.
Technical Context
The SI5338C-B05006-GM integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output, enabling independent integer/fractional frequency generation. Each of its four outputs supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage (1.5–3.3 V).
It features independent phase adjustment (<20 ps step resolution), glitchless frequency increment/decrement (1 ppm steps), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), loss-of-lock and loss-of-signal alarms, and I²C/SMBus configuration - all within a 4 × 4 mm, 24-pin QFN package rated for –40 to +85 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B) |
| Frequency range per output | 0.16–710 MHz (LVPECL/LVDS); up to 350 MHz for SSTL/HSTL; 200 MHz for CMOS |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and GbE jitter requirements |
| Input reference options | Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz), or SSTL/HSTL (5–350 MHz) |
| Supply voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temperature | –40 °C to +85 °C ambient, qualified for industrial applications |
Pinout & Package
SI5338C-B05006-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad (pin 24 = GND). Pin assignments are fixed across Si5338 family variants; this variant includes factory-programmed configuration stored in OTP NVM.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended reference inputs | Support 5–200 MHz CMOS-level clocks; configurable as primary or backup reference |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL |
| VDDO0–VDDO3 | Output buffer supply pins | Independent 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation |
| SCL, SDA | I²C configuration interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; SMBus alert supported |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock, loss-of-signal, or programming completion |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis per output | Enables true zero-ppm accuracy on all four outputs without external VCXOs or crystals |
| Independent output voltage control | Each output bank (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V - eliminates level-shifter ICs |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled increment/decrement - enables dynamic rate adaptation in live systems |
| Programmable phase offset | ±45 ns range in <20 ps steps - allows precise skew alignment across multi-lane SerDes interfaces |
| Spread-spectrum clocking (SSC) | Configurable per-output: 0.5–5.0% down-spread, 33–63 kHz modulation - reduces EMI in dense PCB layouts |
Applications
| PCIe Switch Timing | FPGA Reference Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant reference clocks with matched skew and SSC capability. Use Value: Meets PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS) while eliminating four discrete oscillators and reducing board area by >60%. |
Use Scenario: Supplying configurable 125 MHz LVDS and 250 MHz LVPECL clocks to Xilinx Versal and Intel Agilex FPGAs with mixed I/O banks. IC Role / Device Role / Timing Role: Programmable multi-format clock source supporting simultaneous LVDS, LVPECL, and HCSL outputs at different voltages. Use Value: Eliminates need for separate clock buffers and level translators; enables single-device clock tree for heterogeneous FPGA I/O standards. |
| Broadcast Video Sync | 10GbE Line Card Timing |
Use Scenario: Generating SMPTE ST 2082 (27 Gbps) pixel clock (1.6875 GHz ÷ 16 = 105.46875 MHz) and ancillary sync signals in 4K/8K video processing hardware. IC Role / Device Role / Timing Role: High-precision any-frequency synthesizer with sub-20 ps phase step resolution for frame-accurate timing alignment. Use Value: Achieves <0.7 ps RMS jitter at 105.47 MHz - critical for minimizing bit error rate in SDI and HDMI 2.1 PHY layers. |
Use Scenario: Delivering 156.25 MHz and 312.5 MHz clocks to 10GbE PHYs and MAC controllers in telecom line cards with strict EMI limits. IC Role / Device Role / Timing Role: Dual-frequency, spread-spectrum-capable clock generator supporting both IEEE 802.3ae and ITU-T G.709 timing requirements. Use Value: Enables per-output SSC (0.5–5.0%) to pass CISPR-22 Class B emissions testing without shielding or layout rework. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05006-GM | Same pinout and register map; differs only in factory-programmed NVM configuration (A vs C variant) | Pre-configured for different default output frequencies and formats; requires reprogramming for identical behavior | Select when pre-loaded configuration matches target system boot requirements without I²C initialization |
| LMK04832ISQE/NOPB | Two PLLs, 14 outputs, JESD204B support; higher power (120 mA), larger 64-QFN package | Targeted at RF/data converter timing; lacks per-output SSC and independent VDDO control | Choose for JESD204B deterministic latency or >4 output count; not drop-in for space-constrained PCIe/FPGA designs |
Compared with Si5338A-B05006-GM, SI5338C-B05006-GM offers identical silicon but factory-tuned for distinct output configurations - whereas LMK04832 adds JESD204B features at cost of size, power, and per-output flexibility.
Availability
SI5338C-B05006-GM is available at Aetrix Electronics and suitable for PCIe switch timing, FPGA reference clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338C-B05006-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and broadcast video - designed to replace multiple discrete oscillators with a single programmable IC.
FAQ
What is the factory-programmed configuration of SI5338C-B05006-GM?
The SI5338C-B05006-GM ships with non-volatile memory (OTP) pre-programmed for a specific output configuration - including default frequencies, output formats (e.g., LVDS), voltage levels (VDDO), and spread-spectrum settings. This eliminates mandatory I²C initialization at power-up, enabling immediate clock output after POR. Full reconfiguration remains possible via I²C using ClockBuilder Pro software.
Does SI5338C-B05006-GM support PCIe Gen 4 Common Clock compliance?
Yes, SI5338C-B05006-GM meets PCIe Gen 4 Common Clock jitter requirements (≤0.45 ps RMS, 10 kHz–50 MHz) when configured with appropriate PLL bandwidth (2–5 MHz) and HCSL outputs at 100 MHz. Its 0.7 ps RMS typical jitter and documented PCIe Gen 4 test results in Skyworks AN562 confirm compliance under standard operating conditions.
Can SI5338C-B05006-GM generate four different frequencies simultaneously?
Yes, SI5338C-B05006-GM synthesizes four independent frequencies simultaneously - each output (CLK0–CLK3) is driven by a dedicated MultiSynth™ engine with full fractional-N control. Frequencies can differ by orders of magnitude (e.g., 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz), all with zero-ppm accuracy and sub-20 ps phase step resolution.
What are the power supply requirements for SI5338C-B05006-GM?
SI5338C-B05006-GM requires one core supply (VDD = 1.8 V, 2.5 V, or 3.3 V ±10%) and up to four independent output buffer supplies (VDDO0–VDDO3 = 1.5/1.8/2.5/3.3 V). Typical core current is 45 mA at 100 MHz on all outputs with 25 MHz reference; output buffer current varies by format and frequency (e.g., ≤30 mA per LVPECL output at 710 MHz).
Is SI5338C-B05006-GM pin-compatible with other Si5338 variants?
Yes, all Si5338 variants - including SI5338C-B05006-GM, SI5338A-B05006-GM, and SI5338B-B05006-GM - share identical 24-pin QFN packaging, pinout, register map, and electrical interface. Differences reside solely in factory-programmed OTP content; no PCB or schematic changes are needed when substituting within the Si5338 family.
SI5338C-B05006-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05006-GM FAQ
1.How can I place an order for SI5338C-B05006-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05006-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05006-GM reliable?
The price and inventory of SI5338C-B05006-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05006-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B05006-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05006-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05006-GM?
SI5338C-B05006-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05006-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05006-GM?
For technical support, including SI5338C-B05006-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05006-GM requirements.
6.How does Aetrix verify that SI5338C-B05006-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05006-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05006-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B05006-GM?
All SI5338C-B05006-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05006-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05006-GM part is unused and in its original packaging.
Return procedure for SI5338C-B05006-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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