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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05006-GMR

Name: SI5338C-B05006-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05006-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05006-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05006-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B05006-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05006-GMR datasheet, SI5338C-B05006-GMR pinout, SI5338C-B05006-GMR application, or SI5338C-B05006-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum modulation configurability (0.5–5.0% spread, 33–63 kHz rate), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338C-B05006-GMR implements a two-stage PLL architecture: Stage 1 (synthesis) uses a VCO with Fvco range of ~3.5–7.1 GHz and programmable R/N dividers for reference-to-VCO conversion; Stage 2 (MultiSynth™) employs fractional-N synthesis per output with independent M/P dividers enabling any-frequency generation from 0.16 MHz to 710 MHz. Each output supports integer or fractional mode with <20 ps phase step accuracy.

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers are fully independent-supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, individual VDDO supply selection (1.5–3.3 V), and glitchless frequency increment/decrement in 1 ppm steps via pin or I²C control.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (0.15–0.45 ps RMS)
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently selectable
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail
Temperature Range	–40 to +85 °C; qualified for industrial and telecom line card deployment
Synthesis Resolution	1 ppb frequency step size; enables true zero-ppm accuracy on all outputs

Pinout & Package

SI5338C-B05006-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow standard Si5338 layout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDO rails (VDDO0–VDDO3, VDDO1, VDDO2), core VDD, SCL/SDA/I²C interface, INTR interrupt, and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination
CLK0A, CLK0B	Differential output pair 0	Configurable format (LVPECL/LVDS/HCSL/CML); independent VDDO0 supply (1.5–3.3 V)
VDDO0	Output buffer supply 0	Defines logic levels and drive strength for CLK0A/B; decoupling required per datasheet
SCL, SDA	I²C serial interface	Supports SMBus-compatible programming at up to 400 kHz; enables full register configuration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
Independent output voltage per driver	Each of four output banks supports 1.5 V, 1.8 V, 2.5 V, or 3.3 V VDDO-enables mixed-voltage system interfacing without level shifters
Programmable spread spectrum	Per-output SSC with user-defined spread (0.5–5.0%), modulation rate (33–63 kHz), and center/down-spread mode-reduces EMI in dense PCB layouts
Glitchless frequency adjustment	Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps with <667 ns update time-enables dynamic clock scaling without output interruption
Phase adjustment resolution	<20 ps step accuracy and ±45 ns range per output-supports precise skew alignment in multi-lane SerDes systems (e.g., PCIe, Ethernet)
External feedback mode	Enables zero-delay buffer operation by routing output back to feedback input-eliminates propagation delay in clock distribution trees

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.15–0.45 ps RMS) HCSL clocks compliant with PCIe Gen 4 Common Clock and SRNS requirements. Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane skew (<100 ps) and jitter margin for 16 GT/s link training.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in carrier-grade routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates with zero ppm error using MultiSynth™ integer-mode synthesis. Use Value: Supports multi-rate Ethernet PHYs from same device; reduces BOM count and board area vs. fixed-frequency XO solutions.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (28.63636 MHz), ST 292 (27 MHz), and ST 425 (74.25 MHz) reference clocks to video encoder/decoder ICs in broadcast infrastructure. IC Role / Device Role / Timing Role: Precision clock generator with sub-ppb frequency resolution and <0.7 ps RMS jitter-meeting SMPTE ST 2082-1 jitter mask requirements. Use Value: Enables single-device replacement of multiple crystal oscillators; eliminates timing drift between video/audio subsystems.	Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, 100 MHz PCIe reference, and 50 MHz debug clock to Xilinx Versal or Intel Agilex FPGA platforms. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA timing domains with independent voltage and format per output. Use Value: Simplifies power domain partitioning; avoids external level translators when interfacing to 1.2 V, 1.8 V, and 2.5 V FPGA I/O banks.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.15–0.45 ps RMS) HCSL clocks compliant with PCIe Gen 4 Common Clock and SRNS requirements.

Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane skew (<100 ps) and jitter margin for 16 GT/s link training.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in carrier-grade routers.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates with zero ppm error using MultiSynth™ integer-mode synthesis.

Use Value: Supports multi-rate Ethernet PHYs from same device; reduces BOM count and board area vs. fixed-frequency XO solutions.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (28.63636 MHz), ST 292 (27 MHz), and ST 425 (74.25 MHz) reference clocks to video encoder/decoder ICs in broadcast infrastructure.

IC Role / Device Role / Timing Role: Precision clock generator with sub-ppb frequency resolution and <0.7 ps RMS jitter-meeting SMPTE ST 2082-1 jitter mask requirements.

Use Value: Enables single-device replacement of multiple crystal oscillators; eliminates timing drift between video/audio subsystems.

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, 100 MHz PCIe reference, and 50 MHz debug clock to Xilinx Versal or Intel Agilex FPGA platforms.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA timing domains with independent voltage and format per output.

Use Value: Simplifies power domain partitioning; avoids external level translators when interfacing to 1.2 V, 1.8 V, and 2.5 V FPGA I/O banks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05006-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (A-grade vs C-grade calibration)	Lower jitter floor (0.5 ps RMS typ) and tighter temperature stability; intended for highest-performance PCIe Gen 4/5 and OTN systems	Select when PCIe Gen 4 SRNS jitter margin <0.2 ps RMS is required; otherwise SI5338C-B05006-GMR offers identical functionality at lower cost
ICS854S01IAGLF	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface or MultiSynth™ synthesis	Limited to pre-defined frequencies (e.g., 100/125/156.25 MHz); no spread spectrum or phase adjustment	Choose only for cost-sensitive, static-clock applications where field reconfiguration is unnecessary

Compared with Si5338A-B05006-GM, SI5338C-B05006-GMR delivers identical programmability and feature set at a relaxed jitter specification (0.7 vs 0.5 ps RMS), making it optimal for industrial and telecom line cards where Gen 4 compliance is required but ultra-low jitter is not critical. Against ICS854S01IAGLF, SI5338C-B05006-GMR provides full software-defined frequency agility and advanced timing controls-justifying its use in next-generation reconfigurable platforms.

Availability

SI5338C-B05006-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video synchronization, and FPGA processor clocking requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SI5338C-B05006-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple fixed-frequency crystal oscillators with a single programmable clock generator capable of synthesizing any frequency on four independent outputs-targeting high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video.

FAQ

What is the maximum output frequency supported by SI5338C-B05006-GMR?

The SI5338C-B05006-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined by the internal VCO architecture. All outputs maintain 0.7 ps RMS typical phase jitter within their respective rated ranges.

Does SI5338C-B05006-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338C-B05006-GMR is explicitly specified for PCIe Gen 3 SRNS and Gen 4 Common Clock compliance, with measured RMS jitter of 0.11–0.32 ps (Gen 3 SRNS) and 0.15–0.45 ps (Gen 4 Common Clock) under defined test conditions (PLL BW 2–5 MHz, CDR = 10 MHz). Its MultiSynth™ architecture and low-noise design meet PCI-SIG jitter masks without external filtering.

Can SI5338C-B05006-GMR generate different output voltages on each channel?

Yes, SI5338C-B05006-GMR provides independent VDDO supply pins (VDDO0–VDDO3) for each output bank, allowing individual configuration of 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic levels per channel. This enables direct interfacing to mixed-voltage devices-such as 1.2 V FPGA I/O banks with 2.5 V SerDes receivers-without external level-shifting circuitry.

How is SI5338C-B05006-GMR programmed, and what tools are required?

SI5338C-B05006-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The tool generates custom configuration files, validates timing constraints, and supports in-system programming. No external hardware programmer is needed-only a USB-to-I²C adapter or evaluation board with I²C access is required for development and production programming.

What input reference options does SI5338C-B05006-GMR support?

SI5338C-B05006-GMR accepts six input reference types: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL (5–350 MHz), HSTL (5–350 MHz), and differential (5–710 MHz) signals on dedicated pins (IN1/IN2, IN5/IN6, IN3, IN4). Input impedance and slew rate requirements are documented to ensure optimal jitter performance-e.g., >0.3 V/ns for differential inputs and >1.0 V/ns for single-ended inputs.

SI5338C-B05006-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05006-GMR FAQ

1.How can I place an order for SI5338C-B05006-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05006-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05006-GMR reliable?

The price and inventory of SI5338C-B05006-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05006-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05006-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05006-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05006-GMR?

SI5338C-B05006-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05006-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05006-GMR?

For technical support, including SI5338C-B05006-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05006-GMR requirements.

6.How does Aetrix verify that SI5338C-B05006-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05006-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05006-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05006-GMR?

All SI5338C-B05006-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05006-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05006-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05006-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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