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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05037-GM

Name: SI5338C-B05037-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05037-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05037-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05037-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05037-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C for telecom line card timing applications.

For engineers reviewing the SI5338C-B05037-GM datasheet, SI5338C-B05037-GM pinout, SI5338C-B05037-GM application, or SI5338C-B05037-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet switch use cases, and two technically documented alternative parts with explicit functional and application-level differences.

Technical Context

The SI5338C-B05037-GM implements a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis engines per output. Each engine supports integer or fractional mode, enabling any-frequency generation from 0.16 MHz to 710 MHz with true zero-ppm accuracy.

It features fully independent output drivers supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, programmable per-output supply voltage (1.5–3.3 V), and hardware-based frequency/phase increment/decrement control with <20 ps step resolution and glitchless 1 ppm adjustment capability.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and 10GbE jitter requirements without additional cleanup circuitry
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25/312.5 MHz), PCIe (100 MHz), Fibre Channel (212.5/141.7 MHz), and broadcast video (27/74.25 MHz)
Input Flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables direct replacement of multiple fixed-frequency oscillators
Supply Voltage	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - supports mixed-voltage system clocking with independent output level setting
Package	24-pin QFN, 4 × 4 mm - fits high-density FPGA/ASIC carrier boards with thermal resistance θJA = 37 °C/W
Temperature Range	–40 to +85 °C - qualified for industrial and telecom infrastructure environments
PCIe Compliance	Gen 1/2/3/4 Common Clock; Gen 3 SRNS - validated per PCI-SIG specification with measured TJ < 33.6 ps pk-pk

Pinout & Package

SI5338C-B05037-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin numbering follows top-view orientation with Pin 1 at top-left corner (IN1). All power and ground pins are distributed for low-noise core and output supply decoupling.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair supports separate format and VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank-enables mixed-signal interface (e.g., 1.8 V FPGA + 3.3 V PHY)
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, synthesizers, and control logic; IDD = 45 mA typ @ 100 MHz all outputs
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal; VOL ≤ 0.4 V @ 3 mA sink
GND, RSVD_GND	Ground terminals	Eight dedicated GND pins-including reserved ground-minimize ground bounce and improve jitter performance

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent output clocks, each programmable from 0.16–710 MHz with 1 ppb resolution and zero ppm error
Glitchless Frequency Adjustment	Hardware-controlled frequency increment/decrement in 1 ppm steps with update time ≤ 667 ns (≥18 MHz outputs)
Per-Output Format & Voltage Control	Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with independent VDDO (1.5/1.8/2.5/3.3 V)
Spread Spectrum Clocking (SSC)	Configurable on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, frequency range 5–350 MHz
PCIe Gen 3 SRNS Compliance	Validated 0.11–0.32 ps RMS jitter in Separate Reference No Spread mode per PCI-SIG specification
External Feedback Zero-Delay Mode	Enables synchronous clock distribution with sub-ns skew control via external feedback path

Applications

Ethernet Switch/Routing Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz, 156.25 MHz, and 312.5 MHz clocks for MAC, PHY, and SerDes layers. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter clocks with precise phase alignment across switching fabric and uplink interfaces. Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and meets IEEE 802.3bj jitter limits (≤1.2 ps RMS).	Use Scenario: Server motherboard with CPU, GPU, NVMe SSDs, and add-in cards requiring compliant 100 MHz common clock or SRNS reference. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering Gen 3 SRNS and Gen 4 common clock with validated jitter performance per PCI-SIG test plan. Use Value: Achieves 0.11–0.45 ps RMS jitter across all PCIe generations-enabling full-speed link training without retiming buffers.
Broadcast Video/Audio Timing	Processor & FPGA Clocking
Use Scenario: SMPTE ST 2082/2081 12G-SDI equipment needing exact 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-ns inter-clock skew. IC Role / Device Role / Timing Role: Precision multi-frequency synthesizer generating synchronized video clocks with programmable initial phase offset (±45 ns). Use Value: Enables frame-accurate genlock across multiple video paths using hardware-adjustable phase per output.	Use Scenario: Heterogeneous compute platform with ARM SoC (1.8 V), FPGA (2.5 V), DDR4 memory controller (1.2 V), and peripheral bridges (3.3 V). IC Role / Device Role / Timing Role: Flexible clock hub supplying mixed-voltage, multi-format clocks with independent VDDO and format selection per domain. Use Value: Reduces BOM count by replacing three separate clock ICs; simplifies layout with single 4×4 mm footprint and unified I²C configuration.

Ethernet Switch/Routing Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz, 156.25 MHz, and 312.5 MHz clocks for MAC, PHY, and SerDes layers.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter clocks with precise phase alignment across switching fabric and uplink interfaces.

Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and meets IEEE 802.3bj jitter limits (≤1.2 ps RMS).

Use Scenario: Server motherboard with CPU, GPU, NVMe SSDs, and add-in cards requiring compliant 100 MHz common clock or SRNS reference.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering Gen 3 SRNS and Gen 4 common clock with validated jitter performance per PCI-SIG test plan.

Use Value: Achieves 0.11–0.45 ps RMS jitter across all PCIe generations-enabling full-speed link training without retiming buffers.

Broadcast Video/Audio Timing

Processor & FPGA Clocking

Use Scenario: SMPTE ST 2082/2081 12G-SDI equipment needing exact 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-ns inter-clock skew.

IC Role / Device Role / Timing Role: Precision multi-frequency synthesizer generating synchronized video clocks with programmable initial phase offset (±45 ns).

Use Value: Enables frame-accurate genlock across multiple video paths using hardware-adjustable phase per output.

Use Scenario: Heterogeneous compute platform with ARM SoC (1.8 V), FPGA (2.5 V), DDR4 memory controller (1.2 V), and peripheral bridges (3.3 V).

IC Role / Device Role / Timing Role: Flexible clock hub supplying mixed-voltage, multi-format clocks with independent VDDO and format selection per domain.

Use Value: Reduces BOM count by replacing three separate clock ICs; simplifies layout with single 4×4 mm footprint and unified I²C configuration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and architecture; lacks PCIe Gen 4 common clock validation and has higher typical jitter (0.9 ps RMS vs. 0.7 ps)	Not qualified for PCIe Gen 4 systems; suitable for Gen 1–3 only and non-PCIe applications like MSAN/DSLAM	Select when PCIe Gen 4 compliance is unnecessary and cost optimization is prioritized over lowest jitter.
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; no spread spectrum or phase adjustment	Limited to pre-defined frequencies (e.g., 100/125/156.25 MHz); no dynamic reconfiguration or SSC support	Select only for static clock trees where flexibility and jitter margin are secondary to simplicity and unit cost.

Compared with Si5338A-B-GM and ICS8430I-01LG, the SI5338C-B05037-GM uniquely delivers PCIe Gen 4 readiness, 0.7 ps RMS jitter, and full I²C-based any-frequency synthesis-making it the only option among the three qualified for next-generation server and AI accelerator timing.

Availability

SI5338C-B05037-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B05037-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was engineered for high-performance, software-configurable clock generation in data center, telecom, and broadcast systems-emphasizing ultra-low jitter, multi-protocol compliance, and field-upgradable timing flexibility.

FAQ

What is the primary function of the SI5338C-B05037-GM in a system design?

The SI5338C-B05037-GM serves as an I²C-programmable quad clock generator that replaces up to four discrete oscillators or clock sources. It synthesizes four independent, low-jitter output clocks (0.16–710 MHz) with zero ppm frequency accuracy, supporting PCIe Gen 1–4, Ethernet, and broadcast video timing. Its MultiSynth™ architecture enables flexible, field-reconfigurable clock trees without hardware changes.

Does the SI5338C-B05037-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B05037-GM is validated for PCIe Gen 4 Common Clock mode with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz), meeting PCI-SIG Base Specification 4.0 rev. 0.5 requirements. This validation is explicitly documented in Skyworks' Rev. 1.6 datasheet Table 12 and confirmed via Intel Clock Jitter Tool measurements.

Can the SI5338C-B05037-GM generate different output formats simultaneously?

Yes, the SI5338C-B05037-GM supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs across its four differential pairs. Each output bank (CLK0–CLK3) has an independent VDDO supply (1.4–3.63 V) and format register setting-enabling mixed-signal clocking, such as 1.8 V LVDS for an FPGA and 3.3 V CMOS for a legacy microcontroller.

What is the minimum and maximum input frequency supported by the SI5338C-B05037-GM?

The SI5338C-B05037-GM accepts input frequencies from 5 MHz to 710 MHz depending on interface type: 5–200 MHz for CMOS (IN3/IN4), 5–350 MHz for SSTL/HSTL, and 5–710 MHz for differential inputs (IN1/IN2/IN5/IN6). Crystal inputs are supported from 8–30 MHz with on-chip load capacitance tuning.

How is the SI5338C-B05037-GM programmed and configured in-system?

The SI5338C-B05037-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequency, format, voltage, phase offset, spread spectrum, and status monitoring. Factory-programmed NVM retains settings across power cycles, and runtime updates support dynamic frequency/phase adjustments.

SI5338C-B05037-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05037-GM FAQ

1.How can I place an order for SI5338C-B05037-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05037-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05037-GM reliable?

The price and inventory of SI5338C-B05037-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05037-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05037-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05037-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05037-GM?

SI5338C-B05037-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05037-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05037-GM?

For technical support, including SI5338C-B05037-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05037-GM requirements.

6.How does Aetrix verify that SI5338C-B05037-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05037-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05037-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05037-GM?

All SI5338C-B05037-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05037-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05037-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05037-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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