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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05037-GMR

Name: SI5338C-B05037-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05037-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05037-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05037-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05037-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338C-B05037-GMR datasheet, SI5338C-B05037-GMR pinout, SI5338C-B05037-GMR application, or SI5338C-B05037-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and 24-QFN package with I²C/SMBus interface.

Technical Context

The SI5338C-B05037-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential clocks (5–710 MHz).

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage selection (VDDO0–VDDO3), programmable phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements for high-speed serial links
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and processor/FPGA clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system-level clock sourcing without external buffers
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interface to diverse logic families without level-shifting components
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC/FPGA designs with independent output domain control
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm - space-constrained PCBs with thermal resistance θJA = 37 °C/W

Pinout & Package

SI5338C-B05037-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended CMOS inputs	Support 5–200 MHz CMOS clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply
VDDO0–VDDO3	Output buffer supplies	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for mixed-interface timing domains
SCL, SDA	I²C/SMBus interface	Standard two-wire serial programming; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status pin indicating loss-of-lock or loss-of-signal events
VDD	Core supply	1.8/2.5/3.3 V core power; IDD = 45 mA typ at 100 MHz on all outputs
GND, RSVD_GND	Ground connections	Multiple ground pins minimize noise coupling; RSVD_GND must be connected to GND

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external VCXOs
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode satisfies PCIe Base Spec 3.0 for root complex and endpoint timing
Independent phase adjustment	Programmable ±45 ns offset per output in <20 ps steps - enables precise skew alignment for multi-lane SerDes interfaces
Spread spectrum generation	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions in dense PCB layouts
External feedback mode	Enables zero-delay clock distribution by feeding CLKOUT back to REF_IN - eliminates propagation delay in synchronous fanout
Glitchless frequency tuning	Pin-controlled or I²C-based 1 ppm step increments/decrements - maintains continuous clock output during dynamic frequency scaling

Applications

PCIe Gen 4 Switch Fabric	Ethernet 10GbE Line Card
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized 100 MHz reference clocks with sub-0.5 ps RMS jitter. IC Role / Device Role / Timing Role: Primary clock generator providing Common Clock architecture-compliant outputs to switch die, PHYs, and management MCU. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps, eliminating need for multiple discrete oscillators and reducing BOM count by 75%.	Use Scenario: Dual-port 10GbE line card with XAUI/SGMII interfaces, FPGA-based packet processing, and microcontroller-based management. IC Role / Device Role / Timing Role: Centralized timing source delivering 156.25 MHz (XAUI), 125 MHz (SGMII), 100 MHz (FPGA fabric), and 50 MHz (MCU) from a single device. Use Value: Independent output voltage control (VDDO0 = 2.5 V for LVDS XAUI, VDDO2 = 1.8 V for CMOS MCU) avoids external level shifters and simplifies power domain partitioning.
Broadcast Video Timing	Telecom MSAN Shelf
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz, 74.25 MHz, and 148.5 MHz clocks with tight inter-channel skew. IC Role / Device Role / Timing Role: Precision clock synthesizer generating three video-grade clocks with programmable phase alignment for genlock and frame synchronization. Use Value: Output-output skew < 100 ps and phase adjustment resolution < 20 ps enable sub-pixel timing alignment across multi-channel video paths.	Use Scenario: Multi-service access node (MSAN) supporting DSL, PON, and TDM over a single chassis with strict syncE and IEEE 1588 timing requirements. IC Role / Device Role / Timing Role: Synchronous frequency translator converting GPS-disciplined 10 MHz reference into 1.544 MHz (T1), 2.048 MHz (E1), 155.52 MHz (SONET OC-3), and 622.08 MHz (OC-12) outputs. Use Value: Input-to-output propagation delay < 4 ns and jitter transfer function optimized for syncE Class C ensure compliant timing distribution across legacy and packet-based services.

PCIe Gen 4 Switch Fabric

Ethernet 10GbE Line Card

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized 100 MHz reference clocks with sub-0.5 ps RMS jitter.

IC Role / Device Role / Timing Role: Primary clock generator providing Common Clock architecture-compliant outputs to switch die, PHYs, and management MCU.

Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps, eliminating need for multiple discrete oscillators and reducing BOM count by 75%.

Use Scenario: Dual-port 10GbE line card with XAUI/SGMII interfaces, FPGA-based packet processing, and microcontroller-based management.

IC Role / Device Role / Timing Role: Centralized timing source delivering 156.25 MHz (XAUI), 125 MHz (SGMII), 100 MHz (FPGA fabric), and 50 MHz (MCU) from a single device.

Use Value: Independent output voltage control (VDDO0 = 2.5 V for LVDS XAUI, VDDO2 = 1.8 V for CMOS MCU) avoids external level shifters and simplifies power domain partitioning.

Broadcast Video Timing

Telecom MSAN Shelf

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz, 74.25 MHz, and 148.5 MHz clocks with tight inter-channel skew.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating three video-grade clocks with programmable phase alignment for genlock and frame synchronization.

Use Value: Output-output skew < 100 ps and phase adjustment resolution < 20 ps enable sub-pixel timing alignment across multi-channel video paths.

Use Scenario: Multi-service access node (MSAN) supporting DSL, PON, and TDM over a single chassis with strict syncE and IEEE 1588 timing requirements.

IC Role / Device Role / Timing Role: Synchronous frequency translator converting GPS-disciplined 10 MHz reference into 1.544 MHz (T1), 2.048 MHz (E1), 155.52 MHz (SONET OC-3), and 622.08 MHz (OC-12) outputs.

Use Value: Input-to-output propagation delay < 4 ns and jitter transfer function optimized for syncE Class C ensure compliant timing distribution across legacy and packet-based services.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05037-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-core SoC clock trees where >4 outputs or deterministic latency are required	Select when needing >4 outputs, tighter jitter, or JESD204B compliance; requires different layout and firmware
ICS853S01AG-01LF	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Suitable only for static clock trees where frequencies never change and EMI reduction is not required	Select only for cost-sensitive, fixed-frequency applications with no field reconfiguration needs

Compared with Si5332A-D05037-GM and ICS853S01AG-01LF, the SI5338C-B05037-GMR uniquely balances field-programmability, PCIe Gen 4 readiness, and 4-output flexibility in a compact QFN-making it optimal for mid-complexity systems requiring design reuse and future-proofing without over-engineering.

Availability

SI5338C-B05037-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 infrastructure, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05037-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.

The Si5338 family is designed as a programmable, low-jitter quad clock generator targeting high-speed serial interface timing (PCIe, Ethernet, Fibre Channel) and FPGA/processor clocking in space-constrained, thermally demanding systems.

FAQ

What is the maximum output frequency supported by SI5338C-B05037-GMR?

The SI5338C-B05037-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints.

Does SI5338C-B05037-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B05037-GMR delivers 0.15–0.45 ps RMS jitter in PCIe Gen 4 Common Clock mode (PLL BW 2–5 MHz, CDR = 10 MHz), meeting the PCI-SIG Base Specification 4.0 requirement for total jitter < 33.6 ps pk-pk at 100 MHz HCSL output.

How is SI5338C-B05037-GMR programmed in-system?

SI5338C-B05037-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. Configuration is stored in one-time-programmable (OTP) NVM, enabling pre-programmed devices that boot with valid clocks within 2 ms of power-on.

Can SI5338C-B05037-GMR generate different output voltages on each channel?

Yes, SI5338C-B05037-GMR provides four independent output supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without external level shifters.

What is the thermal performance of SI5338C-B05037-GMR in a 4-layer PCB?

SI5338C-B05037-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. With proper thermal vias under the exposed pad and 1–2 cm² copper pour, it sustains full operation at 85 °C ambient while delivering 45 mA core current and up to 30 mA per output driver.

SI5338C-B05037-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05037-GMR FAQ

1.How can I place an order for SI5338C-B05037-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05037-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05037-GMR reliable?

The price and inventory of SI5338C-B05037-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05037-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05037-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05037-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05037-GMR?

SI5338C-B05037-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05037-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05037-GMR?

For technical support, including SI5338C-B05037-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05037-GMR requirements.

6.How does Aetrix verify that SI5338C-B05037-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05037-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05037-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05037-GMR?

All SI5338C-B05037-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05037-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05037-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05037-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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