Skyworks Solutions Inc. SI5338C-B05078-GM

Overview

SI5338C-B05078-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and MultiSynth™ frequency synthesis supporting any output frequency from 0.16 MHz to 710 MHz. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338C-B05078-GM datasheet, SI5338C-B05078-GM pinout, SI5338C-B05078-GM application, or SI5338C-B05078-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum modulation configurability (0.5–5.0% spread, 33–63 kHz rate), and 24-pin 4×4 mm QFN package compatibility with high-density PCB layouts.

Technical Context

The SI5338C-B05078-GM implements a two-stage PLL architecture: a high-stability input stage locking to external crystal (8–30 MHz) or differential/CMOS references (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesis blocks enabling zero-ppm accuracy on each output. Each synthesis path supports integer or fractional mode operation with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement (1 ppm steps).

Its output stage provides eight configurable terminals (CLK0A/B through CLK3A/B) supporting LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats at per-driver supply voltages from 1.5 V to 3.3 V. Loss-of-lock and loss-of-signal alarms, I²C/SMBus interface, and external feedback mode for zero-delay operation are integrated for system-level timing integrity and diagnostics.

Key Specifications

Pinout & Package

SI5338C-B05078-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C bus), INTR (interrupt output), and GND/RSVD_GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B05078-GM, SI5338C-B05078-GM offers identical hardware but distinct factory firmware-enabling immediate deployment in PCIe Gen 4 systems without reconfiguration. Versus LMK04832ISQE/NOPB, it trades absolute jitter floor for compact size, lower power, and flexible per-output EMI control, making it optimal for space-constrained networking and compute platforms.

Availability

SI5338C-B05078-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video synchronization, and FPGA-based test equipment requiring stable component supply, long-term lifecycle assurance, and guaranteed factory-programmed configurations.

Supply support for SI5338C-B05078-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise frequency synthesis, multi-format output flexibility, and EMI reduction are critical.

FAQ

What is the factory-programmed configuration of the SI5338C-B05078-GM?

The SI5338C-B05078-GM is pre-programmed with a specific output configuration optimized for PCIe Gen 4 applications: four outputs set to 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz respectively, each in HCSL format with 1.8 V VDDO and enabled spread-spectrum modulation. This eliminates the need for initial I²C programming in PCIe-compliant designs.

Does the SI5338C-B05078-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338C-B05078-GM supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical 0.11 ps). It achieves this using a 2–5 MHz PLL bandwidth and 10 MHz CDR reference, as validated per PCI Express Base Specification 4.0 rev. 0.5. Configuration requires I²C register writes to disable spread spectrum and adjust loop filter settings.

Can the SI5338C-B05078-GM generate four different frequencies simultaneously above 350 MHz?

No. The SI5338C-B05078-GM can output only two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-as defined by its MultiSynth™ architecture. Frequencies above 350 MHz must be integer-related harmonics derived from the same VCO; other outputs must be ≤350 MHz or use lower VCO divisions.

What is the maximum allowable input slew rate for low-jitter operation on the SI5338C-B05078-GM?

For optimal jitter performance, the SI5338C-B05078-GM requires ≥0.3 V/ns differential input slew rate on IN1/IN2/IN5/IN6 and ≥1.0 V/ns single-ended slew rate on IN3/IN4. Exceeding these thresholds ensures minimal additive jitter; falling below increases measured RMS jitter beyond the 0.7 ps typical specification.

How does the SI5338C-B05078-GM handle loss-of-signal detection?

The SI5338C-B05078-GM detects loss-of-signal (LOS) on all input pins (IN1–IN6) with 2.6–5 µs latency and releases the alarm in 0.01–1 µs. Detection status is reported via the INTR pin and readable through I²C registers (0x000D[7] and 0x000E[7]). LOS triggers automatic switchover to backup reference if configured, maintaining output continuity.