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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05274-GM

Name: SI5338C-B05274-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05274-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05274-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05274-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B05274-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05274-GM datasheet, SI5338C-B05274-GM pinout, SI5338C-B05274-GM application, or SI5338C-B05274-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338C-B05274-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating outputs from 0.16 MHz to 710 MHz. Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable drive strength and voltage.

It features pin-controlled frequency/phase increment/decrement (667 ns update time >18 MHz), external feedback mode for zero-delay operation, and independent spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread) on any output. The device uses on-chip OTP NVM for configuration storage and supports I²C/SMBus programming via ClockBuilder Pro software.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Synthesis Resolution	1 ppb; enables true zero-ppm frequency accuracy on all four outputs via MultiSynth™ technology.
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V.
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3.

Pinout & Package

The SI5338C-B05274-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff input 1), IN3/IN4 (SE input), IN5/IN6 (diff input 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and GND/RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-compatible; independently configured frequency, format, and voltage (VDDO0).
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis and phase offset <±45 ns.
CLK2A / CLK2B	Differential Output Pair 2	Independent spread-spectrum modulation enabled; usable for PCIe reference clock generation.
CLK3A / CLK3B	Differential Output Pair 3	Supports glitchless frequency adjustment in 1 ppm steps via PINC/FDEC pins.
IN1 / IN2	Differential Input 1	Accepts 5–710 MHz differential clocks; internal 100 Ω termination; slew rate >0.3 V/ns recommended.
IN3 / IN4	Single-Ended Input	Accepts 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD; slew rate >1 V/ns recommended.
VDDO0–VDDO3	Output Buffer Supplies	Each powers one output pair; allows mixed-voltage operation (e.g., 1.8 V LVDS + 3.3 V CMOS).
SCL / SDA	I²C Interface	Standard SMBus-compatible 2-wire bus; supports 400 kHz fast-mode; used for full register configuration.
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS); active-low assertion.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent output clocks synthesized from single reference with 1 ppb resolution and 0 ppm error.
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) verified per PCIe Base Spec 4.0 rev 0.5; supports CDR = 10 MHz.
Independent Output Voltage per Driver	VDDO0–VDDO3 pins enable simultaneous 1.5 V HCSL, 1.8 V LVDS, 2.5 V SSTL, and 3.3 V CMOS outputs.
Glitchless Frequency Adjustment	PINC/FDEC pin control enables 1 ppm step size and 667 ns update time (>18 MHz) without output interruption.
Programmable Spread Spectrum	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, down-spread default.
External Feedback Mode	Enables zero-delay buffer operation using external feedback path; eliminates PLL latency in clock distribution trees.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U server chassis with strict jitter budget (<0.45 ps RMS). IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with matched phase alignment and spread-spectrum capability to reduce EMI. Use Value: Eliminates need for four discrete oscillators; meets PCIe Gen 4 SRNS jitter spec while enabling system-level EMI reduction via programmable SSC.	Use Scenario: Clocking 10 GbE PHYs, packet processors, and SerDes interfaces in carrier-grade Ethernet aggregation switches. IC Role / Device Role / Timing Role: Configurable buffer and level translator generating 156.25 MHz LVDS for PHYs, 125 MHz CMOS for CPUs, and 312.5 MHz HCSL for SerDes lanes. Use Value: Single-device solution supports mixed-signal voltage domains and protocol-specific jitter requirements (GbE RJ <0.79 ps RMS).
Broadcast Video Timing	Telecom Line Card Sync
Use Scenario: Generating SMPTE ST 2082 (28.125 GHz) derived reference clocks (e.g., 74.25 MHz, 148.5 MHz) for 4K/8K video encoders and frame synchronizers. IC Role / Device Role / Timing Role: High-precision frequency translator converting 19.44 MHz OC-12 input to multiple video-standard frequencies with <10 ps pk-pk period jitter. Use Value: Enables multi-format broadcast equipment with zero-ppm synthesis accuracy and sub-1 ps RMS jitter for artifact-free pixel timing.	Use Scenario: Delivering synchronous 2.048 MHz, 8.192 MHz, and 153.6 MHz clocks to TDM framer, packet processor, and SerDes in 3G/4G base station line cards. IC Role / Device Role / Timing Role: Telecom-compliant clock generator supporting EEC Option 1/2 wander tracking and meeting ITU-T G.8262 ePRTC holdover stability. Use Value: Replaces legacy clock trees with integrated jitter cleaning, alarm monitoring (LOL/LOS), and programmable phase offsets for TDM alignment.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U server chassis with strict jitter budget (<0.45 ps RMS).

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with matched phase alignment and spread-spectrum capability to reduce EMI.

Use Value: Eliminates need for four discrete oscillators; meets PCIe Gen 4 SRNS jitter spec while enabling system-level EMI reduction via programmable SSC.

Use Scenario: Clocking 10 GbE PHYs, packet processors, and SerDes interfaces in carrier-grade Ethernet aggregation switches.

IC Role / Device Role / Timing Role: Configurable buffer and level translator generating 156.25 MHz LVDS for PHYs, 125 MHz CMOS for CPUs, and 312.5 MHz HCSL for SerDes lanes.

Use Value: Single-device solution supports mixed-signal voltage domains and protocol-specific jitter requirements (GbE RJ <0.79 ps RMS).

Broadcast Video Timing

Telecom Line Card Sync

Use Scenario: Generating SMPTE ST 2082 (28.125 GHz) derived reference clocks (e.g., 74.25 MHz, 148.5 MHz) for 4K/8K video encoders and frame synchronizers.

IC Role / Device Role / Timing Role: High-precision frequency translator converting 19.44 MHz OC-12 input to multiple video-standard frequencies with <10 ps pk-pk period jitter.

Use Value: Enables multi-format broadcast equipment with zero-ppm synthesis accuracy and sub-1 ps RMS jitter for artifact-free pixel timing.

Use Scenario: Delivering synchronous 2.048 MHz, 8.192 MHz, and 153.6 MHz clocks to TDM framer, packet processor, and SerDes in 3G/4G base station line cards.

IC Role / Device Role / Timing Role: Telecom-compliant clock generator supporting EEC Option 1/2 wander tracking and meeting ITU-T G.8262 ePRTC holdover stability.

Use Value: Replaces legacy clock trees with integrated jitter cleaning, alarm monitoring (LOL/LOS), and programmable phase offsets for TDM alignment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05283-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package (5 × 5 mm).	Preferred for space-constrained designs requiring ultra-low jitter and crystal integration; not drop-in compatible due to pin count and footprint change.	Select when crystal BOM reduction and sub-0.4 ps jitter are mandatory; requires PCB redesign.
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; no I²C interface; 1.2 ps RMS jitter; 3.3 V only; 32-pin TQFP package.	Used in cost-sensitive, static-clock applications where frequency flexibility is unnecessary; lacks spread spectrum, phase control, or multi-voltage outputs.	Select only for legacy designs with unchanging clock trees and no requirement for dynamic reconfiguration or EMI reduction.

Compared with Si5332A-D05283-GM, SI5338C-B05274-GM offers smaller footprint and lower cost but higher jitter and no integrated crystal; versus ICS853S01AGI-01LFT, it provides full programmability and mixed-voltage support at the expense of higher design complexity and BOM count.

Availability

SI5338C-B05274-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature range performance.

Supply support for SI5338C-B05274-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and telecom synchronization, targeting systems requiring precise timing with minimal board space.

FAQ

What is the maximum output frequency supported by SI5338C-B05274-GM in LVPECL format?

The SI5338C-B05274-GM supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10 GbE applications without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints.

Does SI5338C-B05274-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338C-B05274-GM is explicitly specified for PCIe Gen 3 SRNS and Gen 4 Common Clock compliance, with measured RMS jitter of 0.11–0.32 ps (Gen 3 SRNS) and 0.15–0.45 ps (Gen 4 Common Clock) under defined test conditions. SRNS mode requires PLL bandwidth tuning to 2–4 MHz and CDR = 10 MHz, both configurable via I²C registers.

Can SI5338C-B05274-GM generate different output voltages on each of its four output drivers?

Yes, SI5338C-B05274-GM supports independent output supply voltages per driver via dedicated VDDO0–VDDO3 pins, allowing simultaneous 1.5 V HCSL, 1.8 V LVDS, 2.5 V SSTL, and 3.3 V CMOS outputs. This eliminates level-shifting components and simplifies mixed-voltage system timing architectures.

How is configuration stored and retained on SI5338C-B05274-GM after power cycle?

SI5338C-B05274-GM stores configuration in on-chip one-time-programmable (OTP) non-volatile memory (NVM). Upon power-up, the device automatically loads the pre-programmed settings from OTP, enabling immediate clock output without host intervention. Configuration can be updated via I²C and permanently written to OTP using ClockBuilder Pro software.

What input reference types does SI5338C-B05274-GM accept?

SI5338C-B05274-GM accepts six input reference types: (1) 8–30 MHz fundamental-mode crystal (differential), (2) 5–200 MHz CMOS single-ended (IN3/IN4), (3) 5–350 MHz SSTL/HSTL (IN3/IN4), and (4) 5–710 MHz differential (IN1/IN2, IN5/IN6). All inputs support automatic loss-of-signal detection with 2.6–5 µs response time.

SI5338C-B05274-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05274-GM FAQ

1.How can I place an order for SI5338C-B05274-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05274-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05274-GM reliable?

The price and inventory of SI5338C-B05274-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05274-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05274-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05274-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05274-GM?

SI5338C-B05274-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05274-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05274-GM?

For technical support, including SI5338C-B05274-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05274-GM requirements.

6.How does Aetrix verify that SI5338C-B05274-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05274-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05274-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05274-GM?

All SI5338C-B05274-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05274-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05274-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05274-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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