Skyworks Solutions Inc. SI5338C-B05278-GM
- Part No.:
- SI5338C-B05278-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05278-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B05278-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 common clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338C-B05278-GM datasheet, SI5338C-B05278-GM pinout, SI5338C-B05278-GM application, or SI5338C-B05278-GM equivalent, key selection criteria include differential output jitter performance, PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and 24-QFN package compatibility with space-constrained PCB layouts.
Technical Context
The SI5338C-B05278-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four outputs features independent programmable dividers (R, M, P), enabling true zero-ppm frequency accuracy and glitchless 1 ppm frequency increment/decrement via pin or I²C control.
It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and provides independent output voltage per driver (1.5/1.8/2.5/3.3 V), phase adjustment (<20 ps steps), and configurable spread spectrum on any output (5–350 MHz, 0.5–5.0%, 33–63 kHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential outputs (CLK0A/B through CLK3A/B); supports up to 8 single-ended or mixed-mode configurations |
| Frequency range | 0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 common clock and SRNS requirements |
| Input reference | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) |
| Supply voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp | –40 °C to +85 °C ambient, suitable for industrial and telecom line card environments |
Pinout & Package
SI5338C-B05278-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 layout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B–CLK3A/B), six VDDOx supply pins (VDDO0–VDDO3), dual core VDD, SCL/SDA/I²C interface, INTR alarm output, and ground/pad connections.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential output pair 0 | LVPECL/LVDS/HCSL/CML-compatible; independently configured frequency, format, and voltage |
| CLK1A / CLK1B | Differential output pair 1 | Same configurability as CLK0; supports integer/fractional synthesis and phase offset |
| CLK2A / CLK2B | Differential output pair 2 | Independent MultiSynth™ channel; enables simultaneous multi-frequency generation |
| CLK3A / CLK3B | Differential output pair 3 | Fourth fully independent output; supports spread spectrum and glitchless frequency tuning |
| IN1 / IN2, IN5 / IN6 | Differential reference inputs | Accept 5–710 MHz differential clocks; internal 100 Ω termination support |
| IN3 / IN4 | Single-ended reference inputs | Accept 5–200 MHz CMOS-level signals; 20 kΩ internal pull-up/down options |
| VDDO0–VDDO3 | Output buffer supplies | Each powers one output pair; allows mixed-voltage operation across outputs |
| SCL / SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis per output | Enables independent, any-frequency generation (0.16–710 MHz) with zero ppm error and 1 ppb resolution |
| PCIe Gen 4 SRNS compliance | Meets 0.11–0.32 ps RMS jitter requirement under separate reference no-spread conditions, validated per PCI-SIG spec |
| Per-output voltage control | Each of four output drivers supports independent 1.5/1.8/2.5/3.3 V supply, enabling mixed-interface clocking (e.g., LVDS + HCSL) |
| Glitchless frequency tuning | Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption |
| Configurable spread spectrum | On any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, programmable center frequency |
| Loss-of-lock and loss-of-signal detection | Hardware alarms (via INTR pin) with sub-10 ms response time enable real-time system monitoring and fail-safe recovery |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized, low-jitter reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with SRNS-compliant jitter (≤0.32 ps RMS) and independent spread-spectrum control. Use Value: Eliminates need for four discrete oscillators; ensures PCIe link stability and compliance with Gen 4 CDR requirements under varying thermal load. | Use Scenario: Clocking 1 GbE and 10 GbE PHYs, MACs, and packet processors in enterprise switches with mixed voltage interfaces. IC Role / Device Role / Timing Role: Configurable buffer and level translator generating 125 MHz LVDS (for PHYs) and 156.25 MHz CMOS (for processors) from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board area; supports simultaneous differential and single-ended outputs with independent voltage rails. |
| Broadcast Video Timing | Processor & FPGA Clocking |
Use Scenario: Delivering precise, low-phase-noise clocks to SDI serializers, video encoders, and genlock circuits in broadcast infrastructure. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz SMPTE-compliant clocks with <20 ps phase step resolution. Use Value: Enables frame-accurate synchronization across multiple video processing paths; eliminates timing skew between HD/4K/8K signal chains. | Use Scenario: Supplying core, memory, and I/O clocks to heterogeneous SoCs and FPGAs in industrial control and test equipment. IC Role / Device Role / Timing Role: Programmable clock source providing 500 MHz LVDS (FPGA transceivers), 200 MHz HSTL (DDR4 memory), and 100 MHz CMOS (microcontroller peripherals). Use Value: Simplifies clock tree design; avoids external PLLs or fanout buffers while maintaining sub-1 ps jitter on high-speed SerDes lanes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05278-GM | Same pinout and register map; differs only in factory-programmed NVM configuration (default output frequencies and startup behavior) | Identical electrical and timing performance; used where pre-configured boot-up frequencies match system requirements | Select when factory-default settings reduce firmware initialization overhead |
| LMK04832RHAT | Two-stage jitter cleaner architecture; higher power (120 mA typical), larger 48-QFN package; supports JESD204B deterministic latency | Targeted at RF/data converter systems requiring ultra-low additive jitter (<50 fs) and deterministic delay, not general-purpose multi-protocol clocking | Choose only when sub-100 fs additive jitter or JESD204B sync is required; otherwise SI5338C-B05278-GM offers better integration and lower cost |
Compared with Si5338A-B05278-GM, the SI5338C-B05278-GM provides identical hardware functionality but with a different factory OTP image optimized for custom frequency plans; versus LMK04832RHAT, it trades deterministic latency and ultra-low additive jitter for smaller size, lower power, and broader protocol coverage (PCIe, Ethernet, broadcast video) in a single device.
Availability
SI5338C-B05278-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338C-B05278-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed to replace multiple discrete oscillators and clock buffers in high-speed digital systems, delivering programmable, low-jitter timing with minimal footprint and software-defined flexibility.
FAQ
What is the default output configuration of the SI5338C-B05278-GM at power-up?
The SI5338C-B05278-GM boots with factory-programmed OTP settings that configure all four outputs as LVDS at user-defined frequencies stored in non-volatile memory. No external I²C programming is required for basic operation, though ClockBuilder Pro can reconfigure all parameters including format, frequency, and voltage. The SI5338C-B05278-GM retains its last programmed state across power cycles unless explicitly reset or reprogrammed.
Does the SI5338C-B05278-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, the SI5338C-B05278-GM meets PCIe Gen 4 SRNS jitter requirements (≤0.32 ps RMS, 1.5–50 MHz band) when configured with a 2–5 MHz PLL bandwidth and 10 MHz CDR reference. This is verified per PCI-SIG specification using the Skyworks PCIe Clock Jitter Tool and confirmed in Table 12 of the official datasheet. The SI5338C-B05278-GM achieves this with its low-noise MultiSynth™ architecture and optimized loop filter settings.
Can the SI5338C-B05278-GM generate both differential and single-ended outputs simultaneously?
Yes, the SI5338C-B05278-GM supports mixed-mode operation: up to four differential outputs (CLK0A/B–CLK3A/B) and up to eight single-ended outputs (via internal termination and pin remapping), or any combination thereof. For example, CLK0A/B may be configured as LVDS while CLK1A operates as CMOS - each with independent voltage (1.5–3.3 V) and frequency (0.16–200 MHz for CMOS). This capability is documented in the "Highly-configurable output drivers" feature list and Table 6 of the datasheet.
What is the maximum output frequency achievable on a single SI5338C-B05278-GM output channel?
The SI5338C-B05278-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO constraints, as specified in Table 6 Note 6. All outputs maintain 0.7 ps RMS typical jitter at these rates when driven differentially with proper layout and termination.
How does the SI5338C-B05278-GM handle loss-of-signal or loss-of-lock conditions?
The SI5338C-B05278-GM monitors input reference integrity and PLL lock status continuously. Upon loss-of-signal (detection time: 2.6–5 µs) or loss-of-lock (5–10 ms), it asserts the open-drain INTR pin and updates internal status registers. These events trigger automatic failover to backup reference inputs if enabled, and can be polled or interrupted via I²C. The SI5338C-B05278-GM maintains output stability during transient faults and resumes normal operation automatically upon signal restoration.
SI5338C-B05278-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05278-GM FAQ
1.How can I place an order for SI5338C-B05278-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05278-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05278-GM reliable?
The price and inventory of SI5338C-B05278-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05278-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B05278-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05278-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05278-GM?
SI5338C-B05278-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05278-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05278-GM?
For technical support, including SI5338C-B05278-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05278-GM requirements.
6.How does Aetrix verify that SI5338C-B05278-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05278-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05278-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B05278-GM?
All SI5338C-B05278-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05278-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05278-GM part is unused and in its original packaging.
Return procedure for SI5338C-B05278-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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