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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05278-GMR

Name: SI5338C-B05278-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05278-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05278-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05278-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05278-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05278-GMR datasheet, SI5338C-B05278-GMR pinout, SI5338C-B05278-GMR application, or SI5338C-B05278-GMR equivalent, key selection criteria include PCIe jitter compliance, independent per-output voltage (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with board-level thermal management.

Technical Context

The SI5338C-B05278-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ synthesis blocks, each feeding a configurable output driver. Each MultiSynth supports integer or fractional-N division with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement in 1 ppm steps.

It features dual-input flexibility-differential (IN1/IN2, IN5/IN6; 5–710 MHz), single-ended CMOS (IN3/IN4; 5–200 MHz), or crystal (8–30 MHz)-and supports external feedback for zero-delay mode. Loss-of-lock and loss-of-signal alarms are provided via dedicated INTR pin, and all configuration is performed over I²C/SMBus with OTP NVM storage.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock specs
Output Count & Type	4 differential outputs (CLK0A/B through CLK3A/B); supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL
Frequency Range	0.16–710 MHz per output; up to two >350 MHz frequencies simultaneously (Fvco/4 & Fvco/6)
Supply Voltages	Core: 1.8/2.5/3.3 V; independent output buffers: 1.5/1.8/2.5/3.3 V per driver
Synthesis Resolution	1 ppb frequency step size; true zero-ppm accuracy on all outputs via MultiSynth™
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal dissipation
Operating Temp	–40 °C to +85 °C ambient; suitable for industrial and telecom line card environments

Pinout & Package

SI5338C-B05278-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (diff input 1), IN3/IN4 (SE inputs), IN5/IN6 (diff input 2), CLK0A–CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (independent output supply rails), SCL/SDA/INTR (I²C interface and interrupt), and GND/RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination option
IN3 / IN4	Single-ended reference inputs	Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B	Differential output 0	Configurable format (LVPECL/LVDS/HCSL/etc.); independently voltage- and frequency-tuned
CLK1A / CLK1B	Differential output 1	Same flexibility as CLK0; supports phase adjustment <20 ps step resolution
VDDO0 – VDDO3	Per-output buffer supplies	Enable mixed-voltage system timing: e.g., 1.8 V FPGA clock + 3.3 V legacy peripheral clock
SCL / SDA	I²C configuration interface	Standard SMBus-compatible bus; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status pin indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
Independent per-output voltage control	Each of four outputs supports 1.5/1.8/2.5/3.3 V rail-enables direct interfacing with mixed-voltage SoCs/FPGAs without level shifters
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement; no output interruption during real-time clock rate changes
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in dense PCB layouts
Zero-delay mode support	External feedback path enables deterministic latency alignment between input and output clocks for synchronous systems
PCIe Gen 4-compliant jitter	0.15–0.45 ps RMS jitter under Gen 4 common clock conditions-validated per PCI-SIG Base Spec 4.0 rev. 0.5

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter clocks for SerDes lanes, management logic, and PHY interfaces. IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz HCSL, 250 MHz LVDS, 156.25 MHz LVPECL, and 125 MHz CMOS clocks with sub-ps jitter. Use Value: Meets PCIe Gen 4 common clock TJ spec (<33.6 ps pk-pk) and eliminates need for four discrete oscillators-reducing BOM count and layout complexity.	Use Scenario: 10 GbE/25 GbE Ethernet switch fabric with multi-rate SerDes, packet processor, and management MCU. IC Role / Device Role / Timing Role: Frequency translator generating 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), 125 MHz (GbE), and 25 MHz (management) from single 25 MHz crystal. Use Value: Enables single-crystal architecture with zero-ppm synthesis accuracy-improving system frequency stability and simplifying clock tree design.
Broadcast Video Timing	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring precise 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight phase alignment. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering four phase-aligned outputs with <20 ps step resolution and ±45 ns programmable offset. Use Value: Eliminates external delay lines and manual trimming; supports frame-accurate synchronization across multiple video processing pipelines.	Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring flexible clocking for DDR4 memory, transceivers, and logic fabric. IC Role / Device Role / Timing Role: Configurable clock source generating 400 MHz DDR4 clock, 161.1328125 MHz JESD204B, 100 MHz system clock, and 10 MHz reference-all from one device. Use Value: Reduces PCB layer count by consolidating clock sources; supports dynamic reconfiguration via I²C during test mode switching.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter clocks for SerDes lanes, management logic, and PHY interfaces.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz HCSL, 250 MHz LVDS, 156.25 MHz LVPECL, and 125 MHz CMOS clocks with sub-ps jitter.

Use Value: Meets PCIe Gen 4 common clock TJ spec (<33.6 ps pk-pk) and eliminates need for four discrete oscillators-reducing BOM count and layout complexity.

Use Scenario: 10 GbE/25 GbE Ethernet switch fabric with multi-rate SerDes, packet processor, and management MCU.

IC Role / Device Role / Timing Role: Frequency translator generating 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), 125 MHz (GbE), and 25 MHz (management) from single 25 MHz crystal.

Use Value: Enables single-crystal architecture with zero-ppm synthesis accuracy-improving system frequency stability and simplifying clock tree design.

Broadcast Video Timing

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082/ST 2081 video transport system requiring precise 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight phase alignment.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering four phase-aligned outputs with <20 ps step resolution and ±45 ns programmable offset.

Use Value: Eliminates external delay lines and manual trimming; supports frame-accurate synchronization across multiple video processing pipelines.

Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring flexible clocking for DDR4 memory, transceivers, and logic fabric.

IC Role / Device Role / Timing Role: Configurable clock source generating 400 MHz DDR4 clock, 161.1328125 MHz JESD204B, 100 MHz system clock, and 10 MHz reference-all from one device.

Use Value: Reduces PCB layer count by consolidating clock sources; supports dynamic reconfiguration via I²C during test mode switching.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05281-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 32-QFN package	Targeted at next-gen 100G/400G optical modules and AI accelerators requiring >4 clocks	Select when >4 outputs or sub-0.4 ps jitter is required; not drop-in compatible due to pin count and footprint change
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis, no I²C, 1.2 ps RMS jitter	Used in cost-sensitive, static-clocking applications where frequency agility is unnecessary	Choose only for fixed-frequency designs with no need for reprogramming or multi-format outputs

Compared with SI5338C-B05278-GMR, Si5332A-D05281-GM offers greater output count and lower jitter but requires PCB redesign, while ICS8430I-01T sacrifices programmability and flexibility for lower unit cost and simpler validation.

Availability

SI5338C-B05278-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05278-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si5338 family was designed for high-performance, multi-protocol serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, frequency flexibility, and compact integration are critical.

FAQ

What is the maximum output frequency supported by SI5338C-B05278-GMR?

The SI5338C-B05278-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined by the internal VCO architecture. All outputs remain fully programmable within their respective format limits.

Does SI5338C-B05278-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B05278-GMR delivers 0.15–0.45 ps RMS jitter under PCIe Gen 4 common clock test conditions (PLL BW 2–5 MHz, CDR = 10 MHz), meeting the PCI-SIG Base Specification 4.0 rev. 0.5 requirement. This is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 with 100 MHz HCSL outputs.

Can SI5338C-B05278-GMR operate with a single-ended input clock?

Yes, SI5338C-B05278-GMR accepts single-ended CMOS clocks on pins IN3 and IN4 across 5–200 MHz. Input thresholds are VIH = 0.7×VDD and VIL = 0.3×VDD, with 4 pF input capacitance and 20 kΩ input resistance. For optimal jitter, slew rate should exceed 1 V/ns at the input midpoint.

How is configuration stored and retained on SI5338C-B05278-GMR?

SI5338C-B05278-GMR uses one-time-programmable (OTP) non-volatile memory (NVM) to store configuration. After programming via I²C, the device boots automatically with the saved settings. ClockBuilder Pro software generates configuration files that are written directly to OTP, ensuring reliable power-on behavior without external EEPROM or host initialization.

What thermal performance can be expected from SI5338C-B05278-GMR in a 4-layer PCB?

With proper thermal land pattern (IPC Class 2, 10 mm² exposed pad soldered to inner ground plane), SI5338C-B05278-GMR achieves θJA = 37 °C/W in still air. At full load (45 mA core current), junction temperature rise is ~1.7 °C per mW-well within the 150 °C absolute max limit even at 85 °C ambient, assuming ≥2 cm² copper pour under the QFN pad.

SI5338C-B05278-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05278-GMR FAQ

1.How can I place an order for SI5338C-B05278-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05278-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05278-GMR reliable?

The price and inventory of SI5338C-B05278-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05278-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05278-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05278-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05278-GMR?

SI5338C-B05278-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05278-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05278-GMR?

For technical support, including SI5338C-B05278-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05278-GMR requirements.

6.How does Aetrix verify that SI5338C-B05278-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05278-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05278-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05278-GMR?

All SI5338C-B05278-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05278-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05278-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05278-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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