Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05291-GM

Name: SI5338C-B05291-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05291-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338C-B05291-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05291-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,126

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338C-B05291-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05291-GM datasheet, SI5338C-B05291-GM pinout, SI5338C-B05291-GM application, or SI5338C-B05291-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).

Technical Context

The SI5338C-B05291-GM implements a two-stage PLL architecture with a high-frequency VCO and patented MultiSynth™ fractional-N synthesis per output channel. Each of its four output drivers uses independent M/N/P dividers and supports integer or fractional mode operation, enabling true zero-ppm frequency accuracy across all outputs.

It accepts six input references - including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - and provides loss-of-lock and loss-of-signal alarms, independent phase/frequency increment/decrement control (<20 ps step, 1 ppm step), and programmable spread spectrum on any output (0.5–5.0% spread, 33–63 kHz modulation rate).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; LVPECL/LVDS support up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range.
Interface	I²C/SMBus-compatible serial interface; programmable via ClockBuilder Pro software.
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz reference clock.

Pinout & Package

SI5338C-B05291-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, page 33 (Pin Descriptions) and page 37 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination.
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent output channels; each configurable as LVPECL, LVDS, HCSL, CML, SSTL, or HSTL.
VDDO0–VDDO3	Output buffer supply pins	Enable independent voltage setting per output driver (1.5/1.8/2.5/3.3 V).
VDD	Core supply	Single 1.8/2.5/3.3 V supply for internal logic and PLL; PSRR optimized.
SCL, SDA	I²C interface	Standard bidirectional I²C bus (up to 400 kHz) for configuration and status readback.
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events.
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines.

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with zero-ppm precision on all four outputs.
PCIe Gen 4 Common Clock compliance	Meets 0.15–0.45 ps RMS jitter requirement using 2–5 MHz PLL bandwidth and 10 MHz CDR filter.
Independent per-output voltage control	Each of four output drivers supports selectable 1.5/1.8/2.5/3.3 V supply, enabling mixed-voltage system interfacing without level shifters.
Glitchless frequency adjustment	1 ppm step size with pin-controlled or I²C-initiated increment/decrement, avoiding output discontinuities during dynamic reconfiguration.
Programmable spread spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad clock generator delivering four low-jitter HCSL outputs compliant with PCIe Gen 4 Common Clock specification. Use Value: Eliminates need for four discrete oscillators while maintaining <0.45 ps RMS jitter per output, ensuring link training reliability and Gen 4 lane margin.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE PHYs, packet processors, and SerDes in enterprise Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting mixed-rate outputs from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board space vs. discrete oscillators; enables precise phase alignment between data paths via programmable initial phase offset (±45 ns).
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (1.6875 GHz ÷ 4 = 421.875 MHz) and ancillary timing signals to video processing FPGAs and serializers. IC Role / Device Role / Timing Role: High-frequency LVPECL clock generator with sub-ps jitter performance and flexible output formatting. Use Value: Supports >350 MHz outputs (Fvco/4 and Fvco/6 modes) with <1 ps RMS jitter, meeting broadcast-grade jitter budgets for 4K/8K video transport.	Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute acceleration platforms. IC Role / Device Role / Timing Role: Configurable quad-output generator with independent voltage and format per bank (e.g., 1.2 V LVDS for DDR4, 1.8 V HCSL for PCIe, 3.3 V CMOS for peripherals). Use Value: Enables full FPGA clock tree integration from one device, simplifying power sequencing and eliminating inter-clock skew between domains.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad clock generator delivering four low-jitter HCSL outputs compliant with PCIe Gen 4 Common Clock specification.

Use Value: Eliminates need for four discrete oscillators while maintaining <0.45 ps RMS jitter per output, ensuring link training reliability and Gen 4 lane margin.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE PHYs, packet processors, and SerDes in enterprise Ethernet switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer supporting mixed-rate outputs from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and board space vs. discrete oscillators; enables precise phase alignment between data paths via programmable initial phase offset (±45 ns).

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (1.6875 GHz ÷ 4 = 421.875 MHz) and ancillary timing signals to video processing FPGAs and serializers.

IC Role / Device Role / Timing Role: High-frequency LVPECL clock generator with sub-ps jitter performance and flexible output formatting.

Use Value: Supports >350 MHz outputs (Fvco/4 and Fvco/6 modes) with <1 ps RMS jitter, meeting broadcast-grade jitter budgets for 4K/8K video transport.

Use Scenario: Supplying core, memory, and I/O clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute acceleration platforms.

IC Role / Device Role / Timing Role: Configurable quad-output generator with independent voltage and format per bank (e.g., 1.2 V LVDS for DDR4, 1.8 V HCSL for PCIe, 3.3 V CMOS for peripherals).

Use Value: Enables full FPGA clock tree integration from one device, simplifying power sequencing and eliminating inter-clock skew between domains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and architecture; factory-programmed with fixed configuration (non-I²C-programmable OTP).	Used where field reprogramming is unnecessary; lower cost for volume production with static clock trees.	Select SI5338C-B05291-GM when dynamic I²C reconfiguration, spread spectrum tuning, or multi-reference switching is required.
ICS854S01I	Fixed 4-output LVDS generator; no frequency synthesis (only fanout/buffering); max 700 MHz output; no spread spectrum or phase control.	Limited to clock distribution-not synthesis; requires external oscillator(s); no PCIe Gen 4 jitter compliance.	Choose only for simple, low-cost fanout where all frequencies are derived externally and jitter specs are less stringent.

Compared with Si5338A-B-GM and ICS854S01I, the SI5338C-B05291-GM uniquely combines field-programmable any-frequency synthesis, PCIe Gen 4 compliance, per-output voltage/format control, and spread spectrum-enabling single-device replacement of multiple oscillators in high-performance serial interface systems.

Availability

SI5338C-B05291-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05291-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple crystal oscillators with a single programmable clock generator for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-while delivering sub-picosecond jitter and flexible output formatting.

FAQ

What is the maximum output frequency supported by SI5338C-B05291-GM in LVPECL format?

The SI5338C-B05291-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability applies when using Fvco/4 or Fvco/6 synthesis modes, with only two unique frequencies above 350 MHz simultaneously allowed. The SI5338C-B05291-GM achieves this while maintaining 0.7 ps RMS typical phase jitter under specified conditions.

Does SI5338C-B05291-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) timing?

Yes, the SI5338C-B05291-GM is explicitly stated as PCIe Gen 3 SRNS compliant and meets PCIe Gen 4 Common Clock jitter requirements (0.15–0.45 ps RMS). While SRNS mode is not directly listed for Gen 4 in the datasheet, its PLL bandwidth configurability (2–5 MHz) and jitter performance align with Gen 4 SRNS implementation requirements when configured per AN562 and PCIe Base Spec 4.0 rev. 0.5. The SI5338C-B05291-GM supports this via external feedback mode and precise loop filter tuning.

Can SI5338C-B05291-GM generate different output voltages on each of its four channels?

Yes, the SI5338C-B05291-GM provides independent VDDO0–VDDO3 pins, allowing each of its four output drivers to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices-such as 1.2 V FPGA banks, 1.8 V SerDes, and 3.3 V legacy peripherals-without external level shifters. The SI5338C-B05291-GM datasheet confirms this per-output voltage control in the Features section and Table 1.

What crystal frequency ranges are supported by SI5338C-B05291-GM?

The SI5338C-B05291-GM supports external crystals from 8 to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band has specified load capacitance (11–13 pF supported, 17–19 pF recommended), ESR limits (≤300 Ω), and drive level (≤100 µW). These parameters are documented in Tables 8–11 of the Skyworks Rev. 1.6 datasheet for the SI5338C-B05291-GM.

Is ClockBuilder Pro software required to configure SI5338C-B05291-GM?

No, ClockBuilder Pro is optional but strongly recommended for SI5338C-B05291-GM configuration. The device supports standard I²C/SMBus communication for register-level programming, enabling custom firmware integration. However, ClockBuilder Pro provides GUI-based frequency planning, jitter analysis, pin assignment validation, and one-click configuration file generation-significantly accelerating SI5338C-B05291-GM design-in and validation. Skyworks hosts it free at skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software.

SI5338C-B05291-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05291-GM FAQ

1.How can I place an order for SI5338C-B05291-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05291-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05291-GM reliable?

The price and inventory of SI5338C-B05291-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05291-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05291-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05291-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05291-GM?

SI5338C-B05291-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05291-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05291-GM?

For technical support, including SI5338C-B05291-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05291-GM requirements.

6.How does Aetrix verify that SI5338C-B05291-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05291-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05291-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05291-GM?

All SI5338C-B05291-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05291-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05291-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05291-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…