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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05323-GM

Name: SI5338C-B05323-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05323-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05323-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05323-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B05323-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338C-B05323-GM datasheet, SI5338C-B05323-GM pinout, SI5338C-B05323-GM application, or SI5338C-B05323-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN 4×4 mm package with I²C/SMBus programming interface.

Technical Context

The SI5338C-B05323-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm frequency accuracy and programmable phase offset (±45 ns, <20 ps step).

It supports flexible input references (8–30 MHz crystal; 5–710 MHz differential; 5–350 MHz SSTL/HSTL), independent output format selection per channel (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and real-time frequency/phase adjustment via dedicated pins or I²C-enabling glitchless 1 ppm frequency increments and sub-20 ps phase steps without interrupting output clocks.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS)
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Driver Flexibility	Four differential outputs (CLK0A/B–CLK3A/B), eight single-ended, or mixed; independent VDDO per driver (1.5/1.8/2.5/3.3 V)
Spread Spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate
Supply & Temp Range	Core supply: 1.8/2.5/3.3 V ±10%; operating temperature: –40 to +85 °C
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B05323-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are standardized across Si5338 variants and validated per Skyworks Rev. 1.6 datasheet, page 33 (Pin Descriptions) and page 37 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML inputs up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output channels; each pair (e.g., CLK0A/CLK0B) delivers complementary signals
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing
SCL, SDA	I²C/SMBus interface	Standard 2-wire serial interface (up to 400 kHz); supports configuration, status readback, and dynamic tuning
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock (LOL) or loss-of-signal (LOS); active-low

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent, zero-ppm-accurate output frequencies from a single reference-eliminates need for multiple crystals or discrete synthesizers
PCIe Gen 1–4 & SRNS Compliance	Fully satisfies PCIe Gen 3 Separate Reference No Spread (SRNS) and Gen 4 common clock jitter requirements (≤0.45 ps RMS)
Independent Output Voltage Control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs, ASICs, and SerDes
Glitchless Frequency Adjustment	Hardware pin-controlled frequency increment/decrement in 1 ppm steps with ≤667 ns update time-no output interruption during live system tuning
Programmable Phase Offset	±45 ns range per output, adjustable in <20 ps steps-enables precise skew alignment for multi-lane interfaces (e.g., DDR, PCIe)
Spread Spectrum Clocking (SSC)	Per-output SSC with user-selectable spread (0.5–5.0%), rate (33–63 kHz), and direction-reduces EMI without affecting timing margins

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Clock Tree
Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in a server motherboard with PCIe Gen 4 x16 slots. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) and SRNS requirements. Use Value: Eliminates four discrete oscillators; enables single-point frequency/phase tuning across all PCIe domains via I²C; reduces board area and BOM count.	Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric in a carrier-grade L2/L3 switch. IC Role / Device Role / Timing Role: Programmable frequency translator converting a 25 MHz crystal reference into multiple high-frequency Ethernet line rates with deterministic phase relationships. Use Value: Supports IEEE 802.3bj/ck jitter compliance; allows field-upgradable clock configurations via ClockBuilder Pro without hardware change.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: Delivering pixel-clock (74.25 MHz), reference-clock (27 MHz), and audio-clock (48 kHz) to FPGA-based video encoder/decoder modules in broadcast infrastructure gear. IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS, CMOS, and HCSL outputs simultaneously at different voltages (1.8 V, 2.5 V, 3.3 V). Use Value: Single-chip solution replaces three separate clock ICs; independent VDDO per bank avoids level-shifter components; phase alignment ensures clean video sampling.	Use Scenario: Providing stratum-3-compliant 2.048 MHz and 19.44 MHz clocks plus 155.52 MHz SONET/SDH timing to DSPs, transceivers, and framer ICs on a telecom line card. IC Role / Device Role / Timing Role: High-stability clock synthesizer with crystal oscillator input and ultra-low jitter (<1 ps RMS) for synchronous optical network timing. Use Value: Meets OC-12 random jitter spec (≤1 ps RMS); supports external feedback for zero-delay mode; loss-of-signal detection enables failover control.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Clock Tree

Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in a server motherboard with PCIe Gen 4 x16 slots.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) and SRNS requirements.

Use Value: Eliminates four discrete oscillators; enables single-point frequency/phase tuning across all PCIe domains via I²C; reduces board area and BOM count.

Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric in a carrier-grade L2/L3 switch.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a 25 MHz crystal reference into multiple high-frequency Ethernet line rates with deterministic phase relationships.

Use Value: Supports IEEE 802.3bj/ck jitter compliance; allows field-upgradable clock configurations via ClockBuilder Pro without hardware change.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: Delivering pixel-clock (74.25 MHz), reference-clock (27 MHz), and audio-clock (48 kHz) to FPGA-based video encoder/decoder modules in broadcast infrastructure gear.

IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS, CMOS, and HCSL outputs simultaneously at different voltages (1.8 V, 2.5 V, 3.3 V).

Use Value: Single-chip solution replaces three separate clock ICs; independent VDDO per bank avoids level-shifter components; phase alignment ensures clean video sampling.

Use Scenario: Providing stratum-3-compliant 2.048 MHz and 19.44 MHz clocks plus 155.52 MHz SONET/SDH timing to DSPs, transceivers, and framer ICs on a telecom line card.

IC Role / Device Role / Timing Role: High-stability clock synthesizer with crystal oscillator input and ultra-low jitter (<1 ps RMS) for synchronous optical network timing.

Use Value: Meets OC-12 random jitter spec (≤1 ps RMS); supports external feedback for zero-delay mode; loss-of-signal detection enables failover control.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same architecture and pinout; differs in factory-programmed NVM configuration (default output frequencies and formats)	Pre-configured for generic applications; lacks B05323-specific initialization (e.g., PCIe Gen 4 optimized settings)	Select when custom ClockBuilder Pro configuration is preferred over pre-validated PCIe timing profiles
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 0.1–700 MHz range	Not suitable for any-frequency synthesis or dynamic reconfiguration; limited to static clock trees	Choose only for cost-sensitive, unchanging clock requirements where programmability is unnecessary

Compared with SI5338C-B05323-GM, the Si5338A-B-GM offers identical hardware flexibility but requires full ClockBuilder Pro setup for PCIe Gen 4 compliance, whereas the B05323 variant ships with factory-optimized settings. The ICS8430I-01LG provides lower cost and power but sacrifices programmability, phase control, and jitter performance required for Gen 4+ serial links.

Availability

SI5338C-B05323-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, high-density Ethernet switches, broadcast video processing systems, and telecom line cards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05323-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers high-performance, software-programmable clock generation for demanding serial data interfaces-including PCIe, Ethernet, Fibre Channel, and SONET-where ultra-low jitter, multi-output flexibility, and field-reconfigurability are critical.

FAQ

What is the primary function of the SI5338C-B05323-GM in a PCIe Gen 4 system?

The SI5338C-B05323-GM serves as a quad-output clock generator that provides compliant 100 MHz common reference clocks to PCIe Gen 4 endpoints and root complexes. Its 0.45 ps RMS jitter (typical) meets PCIe Gen 4 common clock specifications, and its factory-programmed configuration (B05323) includes optimized PLL bandwidth and spread-spectrum settings for minimal total jitter in high-speed serial link applications. SI5338C-B05323-GM eliminates the need for multiple discrete oscillators while enabling phase alignment across lanes.

Does the SI5338C-B05323-GM support both differential and single-ended output formats simultaneously?

Yes, the SI5338C-B05323-GM supports simultaneous differential and single-ended outputs. It provides four differential output pairs (CLK0A/B through CLK3A/B) and can configure up to eight single-ended outputs using the same pins in CMOS, SSTL, or HSTL modes. Output format, voltage (1.5/1.8/2.5/3.3 V), and termination are independently selectable per channel via I²C registers. SI5338C-B05323-GM's pinout and internal routing allow mixed-mode operation without conflict.

How is the SI5338C-B05323-GM programmed, and what tools are required?

The SI5338C-B05323-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins). Configuration is performed using Skyworks' ClockBuilder Pro software, which generates register maps, validates timing constraints, and exports configuration files for production programming. SI5338C-B05323-GM also supports pin-controlled frequency/phase adjustments (PINC/FDEC/OEB) for real-time tuning without host processor involvement. Factory-programmed NVM retains settings across power cycles.

What input reference options does the SI5338C-B05323-GM accept?

The SI5338C-B05323-GM accepts six input reference types: (1) 8–30 MHz fundamental-mode crystal on IN1/IN2; (2) 5–200 MHz CMOS clock on IN3/IN4; (3) 5–350 MHz SSTL or HSTL on IN3/IN4; (4) 5–710 MHz differential LVDS/LVPECL/CML on IN1/IN2 or IN5/IN6; (5) external feedback for zero-delay mode; and (6) internal oscillator bypass. SI5338C-B05323-GM automatically detects and conditions each source for optimal jitter performance.

Is the SI5338C-B05323-GM pin-compatible with other Si5338 variants?

Yes, the SI5338C-B05323-GM is fully pin-compatible with all Si5338x family members in the 24-QFN package, including Si5338A, Si5338B, and Si5338D variants. Pin functions, electrical characteristics, thermal pad layout, and PCB land pattern are identical across the family. SI5338C-B05323-GM differs only in factory-programmed NVM content and default configuration-hardware integration requires no layout changes when substituting within the Si5338 series.

SI5338C-B05323-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05323-GM FAQ

1.How can I place an order for SI5338C-B05323-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05323-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05323-GM reliable?

The price and inventory of SI5338C-B05323-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05323-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05323-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05323-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05323-GM?

SI5338C-B05323-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05323-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05323-GM?

For technical support, including SI5338C-B05323-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05323-GM requirements.

6.How does Aetrix verify that SI5338C-B05323-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05323-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05323-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05323-GM?

All SI5338C-B05323-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05323-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05323-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05323-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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