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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05323-GMR

Name: SI5338C-B05323-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05323-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05323-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05323-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05323-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338C-B05323-GMR datasheet, SI5338C-B05323-GMR pinout, SI5338C-B05323-GMR application, or SI5338C-B05323-GMR equivalent, key selection criteria include differential output jitter performance at 100 MHz HCSL (0.15–0.45 ps RMS for PCIe Gen 3/4), programmable phase offset (±45 ns), independent output voltage per driver (1.5/1.8/2.5/3.3 V), and 24-pin 4×4 mm QFN package compatibility with PCIe, Ethernet, and FPGA clocking layouts.

Technical Context

The SI5338C-B05323-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four output drivers operates independently with configurable dividers (R/M/N/P), enabling true zero-ppm frequency accuracy across all outputs without shared divider constraints.

It supports flexible input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential inputs - and provides independent output enable (OEB), loss-of-lock (LOL), and loss-of-signal (LOS) status monitoring via dedicated pins (INTR, OEB/PINC/FINC). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML or single-ended CMOS/SSTL/HSTL
Frequency range	0.16–710 MHz per output; supports simultaneous >350 MHz outputs only at Fvco/4 and Fvco/6 (two unique frequencies)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), validated for PCIe Gen 3 SRNS and Gen 4 common clock compliance
Input reference	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Supply & power	Single-core VDD: 1.8/2.5/3.3 V ±10%; typical core current = 45 mA at 100 MHz on all outputs with 25 MHz refclk
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B05323-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is located at top-left (IN1), with pins numbered counter-clockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B (x4 differential pairs)	Differential clock outputs	Each pair supports LVPECL/LVDS/HCSL/CML; independently configurable voltage (1.5–3.3 V) and format
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; decoupling required per bank
VDD	Core supply	1.8/2.5/3.3 V ±10% core rail; 45 mA typical draw; PSRR optimized for noise immunity
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status pin indicating LOL or LOS; pulled up externally
OEB/PINC/FINC	Control inputs	Hardware output enable, phase/frequency increment/decrement triggers (glitchless 1 ppm steps)

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, integer/fractional-N frequency generation on all four outputs with true zero-ppm accuracy and no shared divider limitations
PCIe Gen 1–4 timing compliance	Validated for PCIe Gen 3 SRNS (0.11–0.32 ps RMS) and Gen 4 common clock (0.15–0.45 ps RMS) jitter requirements
Programmable phase adjustment	±45 ns range in <20 ps steps per output, enabling precise skew alignment in multi-lane SerDes systems
Independent output voltage control	Each output bank (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V, allowing mixed-voltage system interfacing without level shifters
Spread spectrum clocking (SSC)	Configurable per output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range - reduces EMI without affecting timing margins
Glitchless frequency tuning	Hardware-triggered frequency increment/decrement in 1 ppm steps with update times as low as 667 ns (for outputs >18 MHz)

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter reference clocks for SerDes lanes and management logic. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 100 MHz HCSL (lane clocks) and 25 MHz CMOS (management) with PCIe Gen 4 SRNS-compliant jitter. Use Value: Eliminates four discrete oscillators; enables per-lane phase alignment via programmable ±45 ns offset; meets Intel's 0.45 ps RMS jitter limit at 100 MHz.	Use Scenario: 10 GbE/25 GbE line card with multi-port PHYs needing scalable, low-noise clock distribution across SERDES, MAC, and packet processor domains. IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz LVDS (PHY), 125 MHz LVPECL (switch fabric), and 25 MHz CMOS (control plane) from one device. Use Value: Reduces board space by 75% vs. discrete oscillators; supports dynamic frequency scaling via I²C; maintains <0.7 ps RMS jitter across all outputs under varying load conditions.
FPGA-Based Video Processing	Telecom Line Card Sync
Use Scenario: Broadcast video encoder FPGA requiring pixel clock (148.5 MHz), reference clock (27 MHz), and DDR memory clock (400 MHz) with tight inter-clock skew control. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct frequencies simultaneously with sub-100 ps output-to-output skew and programmable phase offsets. Use Value: Enables deterministic timing closure across heterogeneous clock domains; avoids external delay lines or PLLs; supports HDMI/SDI timing standards via LVDS/HCSL outputs.	Use Scenario: OTN/SONET line card needing synchronous 155.52 MHz (OC-12), 622.08 MHz (OC-48), and 2.488 GHz (OC-192) clocks derived from a single 19.44 MHz reference. IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner, accepting OC-12 reference and synthesizing higher-rate outputs with 0.7 ps RMS jitter (OC-12 compliant). Use Value: Replaces multiple PLL+VCXO combos; achieves OC-12 random jitter spec (0.7 ps RMS) without external filtering; supports holdover via internal NVM configuration.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter reference clocks for SerDes lanes and management logic.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 100 MHz HCSL (lane clocks) and 25 MHz CMOS (management) with PCIe Gen 4 SRNS-compliant jitter.

Use Value: Eliminates four discrete oscillators; enables per-lane phase alignment via programmable ±45 ns offset; meets Intel's 0.45 ps RMS jitter limit at 100 MHz.

Use Scenario: 10 GbE/25 GbE line card with multi-port PHYs needing scalable, low-noise clock distribution across SERDES, MAC, and packet processor domains.

IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz LVDS (PHY), 125 MHz LVPECL (switch fabric), and 25 MHz CMOS (control plane) from one device.

Use Value: Reduces board space by 75% vs. discrete oscillators; supports dynamic frequency scaling via I²C; maintains <0.7 ps RMS jitter across all outputs under varying load conditions.

FPGA-Based Video Processing

Telecom Line Card Sync

Use Scenario: Broadcast video encoder FPGA requiring pixel clock (148.5 MHz), reference clock (27 MHz), and DDR memory clock (400 MHz) with tight inter-clock skew control.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct frequencies simultaneously with sub-100 ps output-to-output skew and programmable phase offsets.

Use Value: Enables deterministic timing closure across heterogeneous clock domains; avoids external delay lines or PLLs; supports HDMI/SDI timing standards via LVDS/HCSL outputs.

Use Scenario: OTN/SONET line card needing synchronous 155.52 MHz (OC-12), 622.08 MHz (OC-48), and 2.488 GHz (OC-192) clocks derived from a single 19.44 MHz reference.

IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner, accepting OC-12 reference and synthesizing higher-rate outputs with 0.7 ps RMS jitter (OC-12 compliant).

Use Value: Replaces multiple PLL+VCXO combos; achieves OC-12 random jitter spec (0.7 ps RMS) without external filtering; supports holdover via internal NVM configuration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same Si5338 family; differs in factory-programmed configuration (A-grade vs. C-grade calibration; B05323 denotes specific pre-programmed register map)	Requires reprogramming via ClockBuilder Pro for non-default configurations; lacks pre-validated PCIe Gen 4 settings out-of-box	Select when full custom frequency/phase setup is needed and engineering resources exist for configuration validation.
ICS853S01AGI-01LFT	Fixed-frequency quad LVDS clock generator (no I²C, no frequency synthesis); 0.4 ps RMS jitter at 100 MHz but limited to preset outputs	Only suitable where exact frequencies are known pre-design; no runtime reconfiguration or spread spectrum capability	Select for cost-sensitive, static-clock applications where flexibility is unnecessary and jitter margin is critical.

Compared with Si5338A-B-GM, SI5338C-B05323-GMR offers factory-optimized PCIe Gen 4 timing parameters and reduced configuration overhead; compared with ICS853S01AGI-01LFT, it trades fixed-jitter advantage for full frequency/phase programmability and multi-standard compliance.

Availability

SI5338C-B05323-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and FPGA-based video processing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05323-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers high-precision, programmable clock generation for high-speed serial interfaces, designed specifically to replace multiple discrete oscillators while meeting stringent jitter and compliance requirements in PCIe, Ethernet, and telecom systems.

FAQ

What is the factory-programmed configuration of SI5338C-B05323-GMR?

The SI5338C-B05323-GMR is pre-configured with a specific register map optimized for PCIe Gen 4 timing compliance, including default PLL bandwidth (2–5 MHz), output formats (HCSL), and spread spectrum settings. This eliminates initial ClockBuilder Pro setup for standard use cases, though full reprogramming remains supported via I²C. The "B05323" suffix identifies this calibrated variant within the Si5338C family.

Does SI5338C-B05323-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B05323-GMR supports PCIe Gen 4 SRNS mode with 0.15–0.45 ps RMS jitter (1.5–50 MHz band), validated using a 2–5 MHz PLL bandwidth and 10 MHz CDR. Its MultiSynth™ architecture enables independent output configuration, allowing one output to run in SRNS while others serve different protocols - all from a single device.

Can SI5338C-B05323-GMR generate frequencies above 350 MHz on all four outputs simultaneously?

No. SI5338C-B05323-GMR can generate frequencies above 350 MHz (up to 710 MHz) on only two unique outputs simultaneously - specifically at Fvco/4 and Fvco/6. Higher-frequency outputs must share these two synthesis paths; remaining outputs are limited to ≤350 MHz. This constraint is inherent to the VCO architecture and applies regardless of output format.

What is the minimum input clock slew rate required to achieve specified jitter performance for SI5338C-B05323-GMR?

To achieve the datasheet's 0.7 ps RMS jitter specification, SI5338C-B05323-GMR requires a differential input slew rate >0.3 V/ns (measured at midpoint) on IN1/IN2/IN5/IN6, and a single-ended input slew rate >1.0 V/ns on IN3/IN4. Slower slew rates increase deterministic jitter and may degrade PCIe or OC-12 compliance margins.

How does the independent output voltage feature benefit system design with SI5338C-B05323-GMR?

The independent VDDO0–VDDO3 supplies on SI5338C-B05323-GMR allow each output bank to drive different logic families simultaneously - e.g., 1.8 V LVDS for FPGA transceivers, 2.5 V HSTL for memory controllers, and 3.3 V CMOS for microcontrollers - without external level shifters or voltage translators, simplifying power delivery and reducing BOM cost and board area.

SI5338C-B05323-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05323-GMR FAQ

1.How can I place an order for SI5338C-B05323-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05323-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05323-GMR reliable?

The price and inventory of SI5338C-B05323-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05323-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05323-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05323-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05323-GMR?

SI5338C-B05323-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05323-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05323-GMR?

For technical support, including SI5338C-B05323-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05323-GMR requirements.

6.How does Aetrix verify that SI5338C-B05323-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05323-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05323-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05323-GMR?

All SI5338C-B05323-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05323-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05323-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05323-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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