Skyworks Solutions Inc. SI5338C-B05394-GMR

Overview

SI5338C-B05394-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338C-B05394-GMR datasheet, SI5338C-B05394-GMR pinout, SI5338C-B05394-GMR application, or SI5338C-B05394-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage configuration (1.5/1.8/2.5/3.3 V), independent phase/frequency increment/decrement control, spread-spectrum capability (0.5–5.0% down-spread), and 4×4 mm 24-QFN package with 24-pin terminal mapping.

Technical Context

The SI5338C-B05394-GMR implements a two-stage PLL architecture: a high-stability reference stage (input frequency range 5–710 MHz) feeding a programmable VCO, followed by four independent MultiSynth™ fractional-N synthesis blocks-each driving one output pair (CLK0A/B through CLK3A/B). Each MultiSynth supports integer or fractional mode operation with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).

It features dual-mode operation: full PLL-based any-frequency synthesis or low-additive-jitter clock buffer mode (PLL bypass), where input-to-output propagation delay is 2.5–4 ns. Status monitoring includes loss-of-signal (2.6–5 µs detection) and loss-of-lock (5–10 ms) alarms, plus interrupt signaling via INTR pin. Configuration is performed over I²C/SMBus at up to 400 kHz with ClockBuilder Pro software support.

Key Specifications

Pinout & Package

SI5338C-B05394-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: six input pins (IN1–IN6), eight output pins (CLK0A/B–CLK3A/B), four VDDOx supplies (VDDO0–VDDO3), three power pins (VDD, GND, RSVD_GND), two I²C pins (SCL, SDA), one interrupt pin (INTR), and one reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B-GM, SI5338C-B05394-GMR offers full I²C programmability and runtime flexibility; compared with LMK04832RHAR, it trades some jitter margin and output count for smaller footprint and lower power (45 mA vs. 125 mA core current).

Availability

SI5338C-B05394-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, multi-gigabit Ethernet switches, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05394-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise timing, small form factor, and software-defined flexibility are critical.

FAQ

What is the primary function of the SI5338C-B05394-GMR in a system design?

The SI5338C-B05394-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output frequencies from a single input reference. Its core function is to replace multiple discrete oscillators while enabling dynamic frequency/phase tuning, spread-spectrum control, and mixed-signal-format clock distribution-making it ideal for PCIe, Ethernet, and FPGA timing architectures.

Does the SI5338C-B05394-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B05394-GMR is explicitly validated for PCIe Gen 4 Common Clock compliance with ≤0.45 ps RMS jitter (10 kHz–50 MHz) under specified test conditions (PLL BW 2–5 MHz, CDR = 10 MHz). It also meets PCIe Gen 3 SRNS requirements (≤0.32 ps RMS) and supports Gen 1/2/3/4 reference clock generation across all four outputs.

Can the SI5338C-B05394-GMR generate different output voltages simultaneously?

Yes, the SI5338C-B05394-GMR supports independent output buffer supply voltages (VDDO0–VDDO3), allowing simultaneous operation of LVDS at 1.8 V, HCSL at 1.5 V, CMOS at 3.3 V, and LVPECL at 3.3 V-all from the same device. Each VDDO pin powers one differential output pair (CLK0A/B through CLK3A/B), enabling mixed-voltage clock trees without level shifters.

How is the SI5338C-B05394-GMR configured during system startup?

The SI5338C-B05394-GMR boots from factory-programmed OTP memory, delivering pre-defined frequencies and settings within 2 ms of power-on. Full I²C reconfiguration is available post-power-up using ClockBuilder Pro software or custom firmware. The device supports pin-controlled frequency/phase increments (PINC/FDEC) and interrupt-driven status reporting via the INTR pin.

What package type and thermal characteristics does the SI5338C-B05394-GMR have?

The SI5338C-B05394-GMR uses a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 °C to +85 °C ambient. The package supports standard reflow profiles and requires proper PCB land pattern per Skyworks document #9001-001.