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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05520-GM

Name: SI5338C-B05520-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05520-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05520-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05520-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05520-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typical phase jitter), PCIe Gen 1–4 and SRNS-compliant timing, and configurable LVPECL/LVDS/HCSL/CMOS outputs up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface clocking for FPGA, processor, and switch/router applications.

For engineers reviewing the SI5338C-B05520-GM datasheet, SI5338C-B05520-GM pinout, SI5338C-B05520-GM application, or SI5338C-B05520-GM equivalent, key selection criteria include PCIe Gen 4 common-clock jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), 4× differential output drivers, 24-QFN package footprint, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B05520-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each of the four output pairs (CLK0A/B through CLK3A/B) supports independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), voltage supply (VDDO0–VDDO3), phase offset (±45 ns, <20 ps step), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), enabling glitchless frequency adjustment in 1 ppm steps.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each output independently configurable.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V per driver (VDDO0–VDDO3).
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard reflow profiles and high-density PCB layouts.
Operating Temperature	–40 °C to +85 °C ambient - qualified for industrial and telecom line-card environments.

Pinout & Package

SI5338C-B05520-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5338 pinout layout (Rev. 1.6, p. 37), supporting dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B–CLK3A/B), I²C interface (SCL/SDA), interrupt (INTR), and dedicated output supply pins (VDDO0–VDDO3).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination.
CLK0A / CLK0B	Differential output pair 0	Configurable LVPECL/LVDS/HCSL; independently set voltage (VDDO0), format, and phase.
SCL / SDA	I²C/SMBus programming interface	Supports standard-mode (100 kHz) and fast-mode (400 kHz) writes; enables full register configuration.
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events.
VDDO0–VDDO3	Independent output buffer supplies	Enable mixed-voltage system interfacing (e.g., 1.8 V FPGA core + 3.3 V PHY interface).

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external crystals.
PCIe Gen 4 compliance	Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements for Gen 3 - validated per Intel Clock Jitter Tool.
Per-output voltage control	Each of four output banks (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V - eliminates level-shifter ICs in multi-rail systems.
Glitchless frequency tuning	1 ppm-step increment/decrement via PINC/FDEC pins or I²C; update time ≤667 ns above 18 MHz.
Programmable phase offset	±45 ns range with <20 ps resolution per output - enables precise skew alignment across SerDes lanes.

Applications

PCIe Gen 4 Switch Clocking	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock to PCIe Gen 4 switches and attached endpoints in data center top-of-rack systems. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-compliant clocks - one for switch fabric, three for downstream ports. Use Value: Meets PCIe Gen 4 common-clock TJ spec (<33.6 ps pk-pk) and RMS jitter limit (≤0.45 ps), eliminating need for multiple discrete oscillators and reducing BOM count by 75%.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in carrier-grade Ethernet routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing fixed-frequency XO arrays while maintaining sub-1 ps RMS jitter across all rates. Use Value: Enables single-hardware-platform support for multiple Ethernet speeds via software reconfiguration - no PCB respin required.
FPGA Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, 100 MHz PCIe reference, and 50 MHz test/debug clock to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output - matches diverse FPGA I/O standards. Use Value: Eliminates interposer-level clock distribution complexity; supports simultaneous LVDS (I/O), HCSL (PCIe), and CMOS (debug) signaling from one IC.	Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock, AES audio reference (48/96/192 kHz), genlock (10 MHz), and frame sync (29.97 Hz) in 4K/8K broadcast encoders. IC Role / Device Role / Timing Role: Low-jitter, multi-format clock generator with ultra-low deterministic jitter (<10 ps pk-pk) for real-time video processing pipelines. Use Value: Ensures bit-accurate sampling and frame synchronization across HD/SDI, HDMI, and IP video paths - prevents lip-sync drift and packet loss.

PCIe Gen 4 Switch Clocking

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock to PCIe Gen 4 switches and attached endpoints in data center top-of-rack systems.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-compliant clocks - one for switch fabric, three for downstream ports.

Use Value: Meets PCIe Gen 4 common-clock TJ spec (<33.6 ps pk-pk) and RMS jitter limit (≤0.45 ps), eliminating need for multiple discrete oscillators and reducing BOM count by 75%.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in carrier-grade Ethernet routers.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing fixed-frequency XO arrays while maintaining sub-1 ps RMS jitter across all rates.

Use Value: Enables single-hardware-platform support for multiple Ethernet speeds via software reconfiguration - no PCB respin required.

FPGA Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, 100 MHz PCIe reference, and 50 MHz test/debug clock to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output - matches diverse FPGA I/O standards.

Use Value: Eliminates interposer-level clock distribution complexity; supports simultaneous LVDS (I/O), HCSL (PCIe), and CMOS (debug) signaling from one IC.

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock, AES audio reference (48/96/192 kHz), genlock (10 MHz), and frame sync (29.97 Hz) in 4K/8K broadcast encoders.

IC Role / Device Role / Timing Role: Low-jitter, multi-format clock generator with ultra-low deterministic jitter (<10 ps pk-pk) for real-time video processing pipelines.

Use Value: Ensures bit-accurate sampling and frame synchronization across HD/SDI, HDMI, and IP video paths - prevents lip-sync drift and packet loss.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05520-GM	Higher integration: includes integrated crystal, smaller 3 × 3 mm QFN, lower power (32 mA typ), but limited to 3 outputs and max 350 MHz output.	Best suited for space-constrained, lower-frequency applications (e.g., edge compute gateways) where crystal integration reduces bill-of-materials.	Select when board area and crystal BOM reduction outweigh need for fourth output or >350 MHz frequencies.
ICS85411AGI-01LF	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 0.4 ps RMS jitter; 3.3 V only; 32-pin TQFP.	Applicable only in legacy designs requiring static clock fanout - cannot replace crystal oscillators or support frequency translation.	Choose only for simple clock distribution where frequency agility, multi-voltage support, or PCIe Gen 4 compliance are not required.

Compared with Si5332A-D05520-GM and ICS85411AGI-01LF, SI5338C-B05520-GM uniquely delivers full I²C-programmable any-frequency synthesis across four independent outputs at up to 710 MHz, with PCIe Gen 4 compliance and per-output voltage/format control - making it the only option for flexible, high-speed, multi-standard timing in next-gen infrastructure platforms.

Availability

SI5338C-B05520-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch clocking, Ethernet 25G/100G switch timing, and FPGA-based processor clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B05520-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed specifically for high-performance, multi-protocol timing in datacenter, telecom, and broadcast equipment - emphasizing low jitter, software-defined flexibility, and PCIe/SONET/Ethernet compliance.

FAQ

What is the maximum output frequency supported by SI5338C-B05520-GM?

The SI5338C-B05520-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as specified in the functional description section of the datasheet.

Does SI5338C-B05520-GM meet PCIe Gen 4 timing requirements?

Yes, SI5338C-B05520-GM is explicitly validated for PCIe Gen 4 common-clock operation, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) and meeting total jitter limits per PCI-SIG specifications. It also complies with PCIe Gen 3 SRNS requirements and supports CDR rates up to 10 MHz.

How is SI5338C-B05520-GM programmed in-system?

SI5338C-B05520-GM uses an I²C/SMBus-compatible 2-wire interface (SCL/SDA) for full register configuration. Programming is simplified using Skyworks' ClockBuilder Pro software, which generates custom configuration files and supports in-field updates without hardware changes.

Can SI5338C-B05520-GM generate different output voltages on each channel?

Yes - SI5338C-B05520-GM provides four independent output supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices such as 1.8 V FPGAs, 3.3 V PHYs, and 2.5 V memory controllers without external level shifters.

What reference inputs does SI5338C-B05520-GM support?

SI5338C-B05520-GM accepts multiple reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential AC-coupled inputs. Each input path includes dedicated conditioning circuitry and loss-of-signal detection.

SI5338C-B05520-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05520-GM FAQ

1.How can I place an order for SI5338C-B05520-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05520-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05520-GM reliable?

The price and inventory of SI5338C-B05520-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05520-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05520-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05520-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05520-GM?

SI5338C-B05520-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05520-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05520-GM?

For technical support, including SI5338C-B05520-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05520-GM requirements.

6.How does Aetrix verify that SI5338C-B05520-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05520-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05520-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05520-GM?

All SI5338C-B05520-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05520-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05520-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05520-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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