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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05520-GMR

Name: SI5338C-B05520-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05520-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05520-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05520-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05520-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05520-GMR datasheet, SI5338C-B05520-GMR pinout, SI5338C-B05520-GMR application, or SI5338C-B05520-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), programmable phase adjustment (<20 ps steps), spread-spectrum capability (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338C-B05520-GMR implements a two-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) feeding a fractional-N MultiSynth™ synthesizer per output, enabling integer- or fractional-mode synthesis with 1 ppb resolution. Each of the four outputs is independently routed through configurable drivers supporting LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats.

It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references, with independent output enable, glitchless frequency increment/decrement (1 ppm steps), and zero-delay mode via external feedback. The device integrates OTP NVM for factory or field programming and features I²C/SMBus interface with ClockBuilder Pro software support.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Range	8–30 MHz crystal, or 5–710 MHz differential/CMOS/SSTL/HSTL; enables flexible system clock sourcing
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments
PCIe Compliance	Gen 1/2/3/4 Common Clock; Gen 3 SRNS; measured per Intel Clock Jitter Tool v1.6.4

Pinout & Package

SI5338C-B05520-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, with 0.5 mm lead pitch and 0.8 mm max height.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair supports separate format/voltage
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage clock distribution
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise timing operation
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) alarms

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency outputs (0.16–710 MHz) with true zero-ppm accuracy and 1 ppb resolution
Per-output voltage control	Each of four output banks configurable for 1.5/1.8/2.5/3.3 V drive - eliminates level-shifter ICs in multi-rail systems
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution - enables precise skew management across SerDes lanes
Spread-spectrum clocking	Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI peak emissions
Glitchless frequency tuning	Independent frequency increment/decrement (1 ppm steps) via pin or I²C - enables dynamic clock scaling without output interruption

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: High-density 1U switch chassis with multiple PCIe Gen 4 x16 upstream/downstream ports and 10GbE/25GbE PHYs requiring synchronized, low-jitter reference clocks. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks for PCIe root complex and endpoint devices, plus 156.25 MHz for Ethernet PHYs. Use Value: Meets PCIe Gen 4 Common Clock TJ spec (≤33.6 ps pk-pk) and 10GbE jitter requirements (≤1 ps RMS) from a single IC, reducing BOM count and board area.	Use Scenario: Carrier-grade Ethernet aggregation switch supporting 1 GbE, 10 GbE, and 25 GbE interfaces with strict IEEE 802.3 jitter compliance. IC Role / Device Role / Timing Role: Quad-output clock source delivering 125 MHz (1GbE), 156.25 MHz (10GbE), 156.25 MHz (25GbE NRZ), and 312.5 MHz (25GbE PAM4) with independent format/voltage per port. Use Value: Eliminates need for discrete oscillators per interface; supports mixed-signal routing with per-output 1.8 V/2.5 V/3.3 V drive and <0.7 ps RMS jitter.
Broadcast Video Sync Generator	FPGA-Based Telecom Line Card
Use Scenario: SMPTE ST 2059-2 compliant broadcast video router requiring genlock-capable, ultra-low-jitter 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks. IC Role / Device Role / Timing Role: Precision clock synthesizer generating three independent video clocks plus a 10 MHz reference for GPSDO synchronization. Use Value: Achieves <10 ps pk-pk period jitter and supports phase alignment across outputs - critical for frame-accurate video switching and lip-sync.	Use Scenario: 3GPP-compliant small cell baseband unit with FPGA-based digital front-end requiring multiple synchronized clocks for CPRI/OBSAI, ADC/DAC, and MAC processing. IC Role / Device Role / Timing Role: Central timing hub supplying 30.72 MHz (LTE), 122.88 MHz (5G NR), 153.6 MHz (CPRI), and 10 MHz (GPS reference) with programmable phase offsets. Use Value: Enables deterministic latency alignment between RF and baseband domains; supports field reconfiguration via I²C without hardware change.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: High-density 1U switch chassis with multiple PCIe Gen 4 x16 upstream/downstream ports and 10GbE/25GbE PHYs requiring synchronized, low-jitter reference clocks.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks for PCIe root complex and endpoint devices, plus 156.25 MHz for Ethernet PHYs.

Use Value: Meets PCIe Gen 4 Common Clock TJ spec (≤33.6 ps pk-pk) and 10GbE jitter requirements (≤1 ps RMS) from a single IC, reducing BOM count and board area.

Use Scenario: Carrier-grade Ethernet aggregation switch supporting 1 GbE, 10 GbE, and 25 GbE interfaces with strict IEEE 802.3 jitter compliance.

IC Role / Device Role / Timing Role: Quad-output clock source delivering 125 MHz (1GbE), 156.25 MHz (10GbE), 156.25 MHz (25GbE NRZ), and 312.5 MHz (25GbE PAM4) with independent format/voltage per port.

Use Value: Eliminates need for discrete oscillators per interface; supports mixed-signal routing with per-output 1.8 V/2.5 V/3.3 V drive and <0.7 ps RMS jitter.

Broadcast Video Sync Generator

FPGA-Based Telecom Line Card

Use Scenario: SMPTE ST 2059-2 compliant broadcast video router requiring genlock-capable, ultra-low-jitter 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating three independent video clocks plus a 10 MHz reference for GPSDO synchronization.

Use Value: Achieves <10 ps pk-pk period jitter and supports phase alignment across outputs - critical for frame-accurate video switching and lip-sync.

Use Scenario: 3GPP-compliant small cell baseband unit with FPGA-based digital front-end requiring multiple synchronized clocks for CPRI/OBSAI, ADC/DAC, and MAC processing.

IC Role / Device Role / Timing Role: Central timing hub supplying 30.72 MHz (LTE), 122.88 MHz (5G NR), 153.6 MHz (CPRI), and 10 MHz (GPS reference) with programmable phase offsets.

Use Value: Enables deterministic latency alignment between RF and baseband domains; supports field reconfiguration via I²C without hardware change.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05520-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs, smaller 3.2 × 3.2 mm package	Targets higher-port-count systems (e.g., 32-port switches) where space and jitter margin are critical	Select when needing >4 outputs, sub-0.4 ps jitter, or integrated power regulation - not drop-in compatible due to pinout and register map differences
ICS843002AGI-01LFT	Fixed-function quad LVDS clock generator; no I²C programming; 1.2 ps RMS jitter; 2.5 V only	Used in cost-sensitive, static-clocking applications (e.g., legacy storage controllers) where frequency flexibility is unnecessary	Choose only for fixed-frequency, non-reconfigurable designs; lacks Si5338C-B05520-GMR's any-frequency synthesis, spread spectrum, or multi-voltage support

Compared with Si5332A-D05520-GM and ICS843002AGI-01LFT, SI5338C-B05520-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and per-output voltage/format flexibility in a mature, widely deployed 4 × 4 mm footprint - making it optimal for mid-complexity, reconfigurable timing systems where design reuse and supply chain stability matter.

Availability

SI5338C-B05520-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, carrier-grade Ethernet switching, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05520-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 family was designed for high-performance, multi-protocol serial interface timing - specifically targeting PCIe, Ethernet, Fibre Channel, and telecom applications requiring low jitter, programmability, and flexible output configurations.

FAQ

What is the maximum differential input frequency supported by the SI5338C-B05520-GMR?

The SI5338C-B05520-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This allows direct use of high-speed reference clocks such as 622.08 MHz OTN or 709.5 MHz CPRI signals without external division, preserving jitter performance and simplifying system clock tree design.

Does the SI5338C-B05520-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B05520-GMR is explicitly specified for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz band), validated using the Intel Clock Jitter Tool v1.6.4 and meeting PCI-SIG Base Specification 4.0 rev. 0.5 requirements for 100 MHz HCSL outputs.

Can the SI5338C-B05520-GMR generate four different output frequencies simultaneously?

Yes, the SI5338C-B05520-GMR uses independent MultiSynth™ synthesizers per output, enabling four fully independent frequencies - for example, 100 MHz (PCIe), 125 MHz (1GbE), 156.25 MHz (10GbE), and 312.5 MHz (25GbE) - all generated concurrently with zero ppm error and <0.7 ps RMS jitter.

What output voltage levels can be configured per driver on the SI5338C-B05520-GMR?

Each of the four output banks (VDDO0–VDDO3) on the SI5338C-B05520-GMR supports independent supply voltages of 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables mixed-signal systems - such as FPGA-based platforms with 1.8 V transceivers and 3.3 V peripherals - to drive all clocks from a single SI5338C-B05520-GMR without external level shifters.

Is ClockBuilder Pro software required to configure the SI5338C-B05520-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338C-B05520-GMR configuration. The device supports full I²C/SMBus register-level programming, but ClockBuilder Pro provides GUI-driven setup, jitter optimization, PCIe/ETH compliance checking, and one-click configuration file generation - significantly reducing bring-up time versus manual register writes.

SI5338C-B05520-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05520-GMR FAQ

1.How can I place an order for SI5338C-B05520-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05520-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05520-GMR reliable?

The price and inventory of SI5338C-B05520-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05520-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05520-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05520-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05520-GMR?

SI5338C-B05520-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05520-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05520-GMR?

For technical support, including SI5338C-B05520-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05520-GMR requirements.

6.How does Aetrix verify that SI5338C-B05520-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05520-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05520-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05520-GMR?

All SI5338C-B05520-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05520-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05520-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05520-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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