Skyworks Solutions Inc. SI5338C-B05559-GMR

Overview

SI5338C-B05559-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05559-GMR datasheet, SI5338C-B05559-GMR pinout, SI5338C-B05559-GMR application, or SI5338C-B05559-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement capability, <20 ps phase step resolution, and 4×4 mm 24-QFN package with 24-pin terminal mapping.

Technical Context

The SI5338C-B05559-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (PLL) stage (loop bandwidth 1.6 MHz) followed by four independent MultiSynth™ fractional-N synthesis blocks per output. Each MultiSynth supports any-frequency generation from a single VCO (Fvco = 4.85–5.67 GHz), enabling true zero-ppm accuracy on all outputs without external components.

Input flexibility includes eight reference options: differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal. Output configuration supports mixed-mode operation-up to four differential outputs (CLK0A/B through CLK3A/B), eight single-ended clocks, or combinations-with independent format, frequency, voltage, phase offset (±45 ns), and spread-spectrum control per channel.

Key Specifications

Pinout & Package

SI5338C-B05559-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad (GND). Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). All power and ground pins are distributed for low-noise decoupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B-GM, SI5338C-B05559-GMR offers factory-programmed configuration for immediate operation; compared with LMK04832ISQE/NOPB, it provides smaller footprint and lower power at the expense of dual-loop jitter cleaning capability.

Availability

SI5338C-B05559-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10GbE switching platforms, and broadcast video timing systems requiring stable component supply and guaranteed long-term availability.

Supply support for SI5338C-B05559-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple discrete oscillators with a single programmable IC.

FAQ

What is the factory-programmed configuration of the SI5338C-B05559-GMR?

The SI5338C-B05559-GMR is pre-programmed with a specific clock tree configuration stored in one-time-programmable (OTP) memory. This enables immediate operation upon power-up without requiring I²C initialization - unlike blank variants such as Si5338A-B-GM. The exact output frequencies, formats, and voltage settings are defined by Skyworks' B05559 configuration code and are immutable after shipment.

Does the SI5338C-B05559-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B05559-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks' AN562 validation setup using HCSL outputs and appropriate loop bandwidth. Its design includes dedicated PLL bandwidth tuning and jitter filtering optimized for PCIe timing budgets.

Can the SI5338C-B05559-GMR generate frequencies above 350 MHz on all four outputs simultaneously?

No. While the SI5338C-B05559-GMR supports up to 710 MHz per output, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints and internal divider limitations. Other outputs must operate below 350 MHz or at harmonically related lower frequencies.

What is the role of the RSVD_GND pin on the SI5338C-B05559-GMR?

The RSVD_GND pin (Pin 21) is a reserved ground terminal designated for improved thermal and electrical performance in the 24-QFN package. It must be connected to the PCB ground plane with low-inductance routing and is not intended for signal routing or voltage referencing. Leaving it unconnected may degrade PSRR and increase output jitter.

How does the SI5338C-B05559-GMR handle loss-of-signal detection?

The SI5338C-B05559-GMR monitors all six input pins (IN1–IN6) for loss-of-signal (LOS) events with 2.6–5 µs detection time and 0.01–1 µs release time. When triggered, it asserts the INTR pin and updates internal status registers. LOS detection is disabled in PLL bypass (clock buffer) mode below 5 MHz but remains functional for all supported input types above that threshold.