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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05574-GM

Name: SI5338C-B05574-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05574-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05574-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05574-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05574-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with independent any-frequency synthesis on four differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05574-GM datasheet, SI5338C-B05574-GM pinout, SI5338C-B05574-GM application, or SI5338C-B05574-GM equivalent, key selection considerations include its MultiSynth™-based fractional-N PLL architecture, per-output voltage configurability (1.5–3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum support (0.5–5.0% at 33–63 kHz), and PCIe/10GbE/Ethernet switch timing validation.

Technical Context

The SI5338C-B05574-GM implements a two-stage synthesis architecture: a primary PLL (1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers generating output frequencies from 0.16 MHz to 710 MHz. Each output stage supports format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and dedicated VDDO supply.

It features loss-of-lock and loss-of-signal alarms, programmable initial phase offset (±45 ns), glitchless frequency increment/decrement via pin or I²C, and external feedback mode for zero-delay operation. The device uses on-chip OTP NVM for configuration storage and supports ClockBuilder Pro for register-level programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and 10GbE jitter requirements with differential outputs
Output Frequency Range	0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board design with per-output level translation
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - surface-mount compatible with standard reflow profiles and low thermal resistance (θJA = 37 °C/W)
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Core Supply Current	45 mA typ at 100 MHz on all outputs - enables low-power timing in power-constrained embedded systems

Pinout & Package

SI5338C-B05574-GM is housed in a 24-lead, 4 × 4 mm, 0.5 mm pitch QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), and pin numbering proceeds counterclockwise. The package supports standard PCB land patterns per JEDEC MO-220.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept AC-coupled differential reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-Ended Inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential Output Pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair configurable for format and VDDO
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output bank enable mixed-signal voltage domain interfacing
VDD	Core Supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for clean internal PLL operation
SCL, SDA	I²C Interface	SMBus-compatible 100/400 kHz control bus; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock, loss-of-signal, or other fault conditions
OEB, PINC, FINC	Control Inputs	Hardware pins for output enable, frequency increment/decrement, and phase increment/decrement with glitchless updates

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N dividers enabling true zero-ppm accuracy across any output frequency combination
PCIe Gen 1–4 Compliance	Validated for Common Clock and Gen 3 SRNS modes; meets PCIe Gen 4 RMS jitter ≤0.45 ps (10 kHz–50 MHz)
Per-Output Voltage Control	Each of four output banks supports independent VDDO (1.5/1.8/2.5/3.3 V) for direct interfacing with diverse logic families
Glitchless Frequency Tuning	Hardware-controlled frequency increment/decrement in 1 ppm steps without output interruption or phase discontinuity
Programmable Spread Spectrum	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, selectable up/down/center spread
External Feedback Mode	Enables zero-delay buffer operation by routing an output back to the feedback input, eliminating propagation delay

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support and spread spectrum. Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and ensures deterministic inter-clock skew <100 ps.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in Layer 2/3 switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer configured for IEEE 802.3 compliant Ethernet timing with jitter <0.7 ps RMS. Use Value: Supports multi-rate Ethernet interfaces on a single chip; avoids external jitter cleaners and simplifies BOM.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 297 MHz and ST 2081 (6G-SDI) 148.5 MHz clocks with sub-1 ps jitter to video encoder/decoder ASICs. IC Role / Device Role / Timing Role: High-precision quad clock source with independent phase alignment for multi-link video synchronization. Use Value: Enables frame-accurate genlock across multiple video channels using programmable phase offsets (±45 ns resolution).	Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 500 MHz processor, 1600 MT/s DDR4, 48 MHz USB) to Xilinx Zynq or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable clock generator supporting mixed-format outputs (LVDS for DDR, HCSL for PCIe, CMOS for peripherals). Use Value: Replaces multiple discrete clock ICs; simplifies FPGA clock tree design and improves timing margin via low additive jitter.

PCIe Gen 3/4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support and spread spectrum.

Use Value: Eliminates need for four discrete oscillators; reduces board area by >60% and ensures deterministic inter-clock skew <100 ps.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in Layer 2/3 switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer configured for IEEE 802.3 compliant Ethernet timing with jitter <0.7 ps RMS.

Use Value: Supports multi-rate Ethernet interfaces on a single chip; avoids external jitter cleaners and simplifies BOM.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 297 MHz and ST 2081 (6G-SDI) 148.5 MHz clocks with sub-1 ps jitter to video encoder/decoder ASICs.

IC Role / Device Role / Timing Role: High-precision quad clock source with independent phase alignment for multi-link video synchronization.

Use Value: Enables frame-accurate genlock across multiple video channels using programmable phase offsets (±45 ns resolution).

Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 500 MHz processor, 1600 MT/s DDR4, 48 MHz USB) to Xilinx Zynq or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable clock generator supporting mixed-format outputs (LVDS for DDR, HCSL for PCIe, CMOS for peripherals).

Use Value: Replaces multiple discrete clock ICs; simplifies FPGA clock tree design and improves timing margin via low additive jitter.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and architecture; differs only in factory-programmed OTP configuration (different default frequency plan and I²C address)	Pre-configured for specific legacy reference designs; lacks the B05574 custom configuration for PCIe Gen 4 common clock + 10GbE dual-rate use case	Select SI5338C-B05574-GM when requiring out-of-box support for simultaneous 100 MHz PCIe and 156.25 MHz Ethernet clocks with matched phase alignment.
LMK04832RHAR	Two PLLs + eight outputs; higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency	Targeted at RF/data converter timing; includes dual-loop jitter cleaning not needed in pure clock generation applications	Choose LMK04832RHAR only if deterministic latency, ultra-low jitter (<0.1 ps RMS), or >4 outputs are required-otherwise SI5338C-B05574-GM offers superior cost, size, and power efficiency.

Compared with Si5338A-B-GM, SI5338C-B05574-GM delivers application-specific pre-programming for PCIe Gen 4 and 10GbE co-timing, while versus LMK04832RHAR it provides 63% lower power and 58% smaller footprint at the expense of JESD204B features irrelevant to switch/router timing.

Availability

SI5338C-B05574-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE Ethernet routing, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05574-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 family is designed as a highly configurable, low-jitter clock generator platform targeting high-speed serial interface timing in networking, data center, and broadcast equipment-emphasizing flexibility, integration, and PCIe/10GbE compliance.

FAQ

What is the factory configuration of SI5338C-B05574-GM?

The SI5338C-B05574-GM is pre-programmed with a custom OTP configuration optimized for PCIe Gen 4 common clock (100 MHz) and 10GbE Ethernet (156.25 MHz) dual-output operation, including matched phase alignment, HCSL output format, and 3.3 V VDDO settings. This eliminates the need for initial I²C programming in those target applications.

Does SI5338C-B05574-GM support spread-spectrum clocking (SSC)?

Yes, SI5338C-B05574-GM supports fully programmable spread-spectrum clocking on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and spread type (down, center, or up). Default is 0.5% down spread at ~31.5 kHz, and configuration is stored in OTP or updated dynamically via I²C.

Can SI5338C-B05574-GM generate frequencies above 350 MHz?

Yes, SI5338C-B05574-GM supports frequencies up to 710 MHz on LVPECL/LVDS outputs, but only two unique frequencies above 350 MHz may be active simultaneously (Fvco/4 and Fvco/6). Higher frequencies require integer-mode MultiSynth operation and careful VCO calibration per the datasheet's synthesis stage constraints.

What input references does SI5338C-B05574-GM accept?

SI5338C-B05574-GM accepts six input reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). Input selection is configurable via I²C registers, and automatic input detection is not supported.

Is SI5338C-B05574-GM pin-compatible with other Si5338 variants?

Yes, all Si5338 variants-including SI5338C-B05574-GM-are pin-compatible across the family and share identical 24-QFN packaging, pin assignments, and power sequencing requirements. Differences exist only in OTP configuration, not hardware interface or electrical behavior.

SI5338C-B05574-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05574-GM FAQ

1.How can I place an order for SI5338C-B05574-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05574-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05574-GM reliable?

The price and inventory of SI5338C-B05574-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05574-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05574-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05574-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05574-GM?

SI5338C-B05574-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05574-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05574-GM?

For technical support, including SI5338C-B05574-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05574-GM requirements.

6.How does Aetrix verify that SI5338C-B05574-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05574-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05574-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05574-GM?

All SI5338C-B05574-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05574-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05574-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05574-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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