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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05574-GMR

Name: SI5338C-B05574-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05574-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05574-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05574-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05574-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and 10 GbE timing systems.

For engineers reviewing the SI5338C-B05574-GMR datasheet, SI5338C-B05574-GMR pinout, SI5338C-B05574-GMR application, or SI5338C-B05574-GMR equivalent, this page delivers verified specifications including MultiSynth™-based any-frequency synthesis (0.16–710 MHz), independent output voltage per driver (1.5–3.3 V), spread-spectrum control (0.5–5.0% at 33–63 kHz), and loss-of-lock/loss-of-signal alarms - all confirmed for the exact SI5338C-B05574-GMR variant.

Technical Context

The SI5338C-B05574-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving one output pair (CLKxA/CLKxB). Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential clocks (5–710 MHz).

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable voltage (1.5/1.8/2.5/3.3 V), independent phase adjustment (<20 ps steps), and glitchless frequency increment/decrement in 1 ppm steps. External feedback mode enables zero-delay operation, and status monitoring includes INTR pin assertion for loss-of-lock and loss-of-signal events.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports integer/fractional synthesis with true zero-ppm accuracy on all outputs.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - no external PLL required.
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per driver.
Package & Pins	24-pin QFN, 4 × 4 mm; 4 differential output pairs (CLK0A/B to CLK3A/B), 6 inputs (IN1–IN6), I²C interface (SCL/SDA), interrupt (INTR).
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment.
Spread Spectrum	Configurable per output: 0.5–5.0% down-spread at 33–63 kHz modulation rate - reduces EMI without altering system timing margins.

Pinout & Package

SI5338C-B05574-GMR is housed in a thermally enhanced 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND), and pin 13 is center-bottom (CLK3A).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; internal 100 Ω termination support.
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); slew-rate sensitive for jitter optimization.
CLK0A–CLK3B	Differential output pairs	Four independent output channels; each pair supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL with selectable VDDO.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output group - enables mixed-voltage system interfacing.
SCL, SDA	I²C serial interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro configuration.
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock, loss-of-signal, or PLL unlock events.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 0 ppm precision per output.
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 rev. 0.5 common clock jitter limits (0.15–0.45 ps RMS) without external filtering.
Glitchless frequency tuning	Hardware-supported 1 ppm step frequency increment/decrement via PINC/FDEC pins - no software reprogramming needed.
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps resolution - enables precise skew alignment across multi-lane interfaces.
Zero-delay mode	External feedback path allows bypassing internal PLL for deterministic propagation delay (2.5–4 ns) in clock buffer applications.

Applications

Ethernet Switch/Router Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-density 10 GbE/25 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 250 MHz (PHY reference) with sub-ps jitter. Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 4 jitter compliance and enabling dynamic frequency scaling for power-aware link training.	Use Scenario: Server motherboard with dual CPU sockets, multiple PCIe slots (Gen 3/4), and integrated CXL memory controllers. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe refclk, 100 MHz CXL refclk, 125 MHz USB 3.x, and 25 MHz management bus clock - all from one device. Use Value: Reduces BOM count and layout complexity while meeting PCIe Gen 4 SRNS (0.11–0.32 ps RMS) and Intel Clock Jitter Tool validation requirements.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2059-2 compliant IP video encoder/decoder handling 4K60 UHD streams with AES67 audio embedding. IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 48 kHz audio word clock - all traceable to GPS-disciplined 10 MHz reference. Use Value: Achieves <10 ps pk-pk period jitter and supports IEEE 1588 PTP timestamp alignment via programmable phase offset per output.	Use Scenario: Industrial FPGA-based motion controller with ARM Cortex-A9 processor, DDR3 memory, Gigabit Ethernet, and real-time I/O expansion. IC Role / Device Role / Timing Role: Central timing hub supplying 100 MHz FPGA logic clock, 400 MHz DDR3 interface clock, 125 MHz GMII clock, and 32.768 kHz RTC clock - all from single Si5338C-B05574-GMR. Use Value: Enables deterministic clock domain crossing, eliminates inter-clock skew, and simplifies power sequencing with single-core supply (1.8/2.5/3.3 V).

Ethernet Switch/Router Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-density 10 GbE/25 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 250 MHz (PHY reference) with sub-ps jitter.

Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 4 jitter compliance and enabling dynamic frequency scaling for power-aware link training.

Use Scenario: Server motherboard with dual CPU sockets, multiple PCIe slots (Gen 3/4), and integrated CXL memory controllers.

IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe refclk, 100 MHz CXL refclk, 125 MHz USB 3.x, and 25 MHz management bus clock - all from one device.

Use Value: Reduces BOM count and layout complexity while meeting PCIe Gen 4 SRNS (0.11–0.32 ps RMS) and Intel Clock Jitter Tool validation requirements.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2059-2 compliant IP video encoder/decoder handling 4K60 UHD streams with AES67 audio embedding.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 48 kHz audio word clock - all traceable to GPS-disciplined 10 MHz reference.

Use Value: Achieves <10 ps pk-pk period jitter and supports IEEE 1588 PTP timestamp alignment via programmable phase offset per output.

Use Scenario: Industrial FPGA-based motion controller with ARM Cortex-A9 processor, DDR3 memory, Gigabit Ethernet, and real-time I/O expansion.

IC Role / Device Role / Timing Role: Central timing hub supplying 100 MHz FPGA logic clock, 400 MHz DDR3 interface clock, 125 MHz GMII clock, and 32.768 kHz RTC clock - all from single Si5338C-B05574-GMR.

Use Value: Enables deterministic clock domain crossing, eliminates inter-clock skew, and simplifies power sequencing with single-core supply (1.8/2.5/3.3 V).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05574-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration - A-grade uses different default startup frequencies and spread-spectrum settings.	Not suitable for designs requiring the exact preconfigured output frequencies and SSC parameters of SI5338C-B05574-GMR.	Select only if ClockBuilder Pro reprogramming is part of production flow and startup behavior can be fully validated.
LMK04832RHAT	Two PLLs (not four independent synthesizers); higher power (120 mA vs. 45 mA typ); larger 48-QFN package; supports JESD204B deterministic latency but lacks MultiSynth™ any-frequency flexibility.	Preferred for JESD204B-compliant RF sampling systems; not drop-in for PCIe Gen 4 or broadcast video where four independent low-jitter outputs are mandatory.	Choose when deterministic latency and dual-loop redundancy outweigh need for compact size and ultra-low jitter across four arbitrary frequencies.

Compared with SI5338C-B05574-GMR, the Si5338A-B05574-GMR requires full reconfiguration to match startup behavior, while the LMK04832RHAT trades pin count and jitter performance for JESD204B features - making SI5338C-B05574-GMR optimal for space-constrained, multi-protocol timing consolidation where zero-ppm synthesis and sub-ps jitter are non-negotiable.

Availability

SI5338C-B05574-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clocking, and broadcast video/audio synchronization requiring stable component supply, long-term lifecycle support, and guaranteed factory programming consistency.

Supply support for SI5338C-B05574-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple fixed-frequency oscillators while supporting PCIe, Ethernet, Fibre Channel, and broadcast video timing standards.

FAQ

What is the factory-programmed configuration of the SI5338C-B05574-GMR?

The SI5338C-B05574-GMR ships with pre-programmed NVM settings optimized for PCIe Gen 4 common clock operation: four HCSL outputs at 100 MHz, 100 MHz, 100 MHz, and 25 MHz, with 0.5% down-spread enabled on the primary 100 MHz output. All registers retain full I²C reprogrammability post-power-up, and ClockBuilder Pro supports custom configuration export/import for SI5338C-B05574-GMR.

Does the SI5338C-B05574-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338C-B05574-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–4 MHz and CDR set to 10 MHz. This is validated per PCI-Express Base Specification 4.0 rev. 0.5 using differential HCSL outputs and low-noise differential reference input - a capability confirmed for the SI5338C-B05574-GMR variant in Skyworks' AN562 application note.

Can the SI5338C-B05574-GMR generate four different frequencies above 350 MHz simultaneously?

No. The SI5338C-B05574-GMR can output only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. Higher-frequency outputs must share one of those two values; remaining outputs must be ≤350 MHz. This limitation applies identically across all Si5338 variants, including SI5338C-B05574-GMR, and is documented in Section 3.3 "Synthesis Stages" of the datasheet.

What is the maximum output current per VDDO rail on the SI5338C-B05574-GMR?

The SI5338C-B05574-GMR supports up to 30 mA per VDDO rail under worst-case conditions (LVPECL at 710 MHz), with typical consumption ranging from 6 mA (CMOS at 50 MHz, 15 pF load) to 20 mA (HCSL at 250 MHz, 2 pF load). Total output current is limited by thermal design; the device's θJA of 37 °C/W requires proper PCB copper pour and thermal via placement beneath the exposed pad to sustain full-load operation at +85 °C ambient.

How does the SI5338C-B05574-GMR handle loss-of-signal detection on its input clocks?

The SI5338C-B05574-GMR detects loss-of-signal (LOS) on any active input within 2.6–5 µs (typ/max), releasing the alarm within 0.01–1 µs after signal restoration. LOS status is reported via the INTR pin and readable through I²C register 0x000D. This behavior is identical across all Si5338 variants and confirmed for SI5338C-B05574-GMR in Table 5 of the Rev. 1.6 datasheet - enabling fast failover in redundant clock architectures.

SI5338C-B05574-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05574-GMR FAQ

1.How can I place an order for SI5338C-B05574-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05574-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05574-GMR reliable?

The price and inventory of SI5338C-B05574-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05574-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05574-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05574-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05574-GMR?

SI5338C-B05574-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05574-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05574-GMR?

For technical support, including SI5338C-B05574-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05574-GMR requirements.

6.How does Aetrix verify that SI5338C-B05574-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05574-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05574-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05574-GMR?

All SI5338C-B05574-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05574-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05574-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05574-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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