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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05575-GMR

Name: SI5338C-B05575-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05575-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05575-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05575-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05575-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338C-B05575-GMR datasheet, SI5338C-B05575-GMR pinout, SI5338C-B05575-GMR application, or SI5338C-B05575-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe Gen 4 jitter performance (0.15–0.45 ps RMS), exact 24-QFN package mapping, and two field-validated alternative parts with documented functional trade-offs.

Technical Context

The SI5338C-B05575-GMR implements a dual-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2 that generate any-frequency outputs with true zero-ppm accuracy. Each output driver supports independent voltage selection (1.5/1.8/2.5/3.3 V) and format configuration.

It features glitchless frequency increment/decrement in 1 ppm steps, programmable phase offset (±45 ns, <20 ps step resolution), and configurable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation rate) on any output. Loss-of-lock and loss-of-signal alarms are provided via dedicated INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 common clock spec (0.15–0.45 ps RMS)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per VDDOx rail
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card use

Pinout & Package

SI5338C-B05575-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flank leads and an exposed thermal pad (pin 24). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C) and provides low thermal resistance (θ_JA = 37 °C/W).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent output drivers; each configurable for format, voltage, and enable via I²C
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output bank; decoupling required per rail
VDD	Core supply	1.8/2.5/3.3 V ±10%; typical core current = 45 mA at 100 MHz on all outputs
SCL/SDA	I²C interface	SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal events
RSVD_GND	Reserved ground	Internally connected to die substrate; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency outputs with 0 ppm error and 1 ppb resolution
PCIe Gen 4 compliance	Validated 0.15–0.45 ps RMS jitter in common clock mode per PCIe Base Spec 4.0 rev 0.5
Glitchless frequency tuning	Hardware-supported 1 ppm step frequency increment/decrement without output interruption
Programmable phase alignment	±45 ns range with <20 ps step resolution per output, enabling precise skew control in multi-lane systems
Configurable spread spectrum	Per-output SSC with adjustable spread (0.5–5.0%), rate (33–63 kHz), and direction (down/up/center)
Flexible reference inputs	Six input options including crystal oscillator, single-ended CMOS, and high-speed differential signals up to 710 MHz

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent enable/disable and SSC control per lane group. Use Value: Meets PCIe Gen 4 common clock jitter requirement (≤0.45 ps RMS) while eliminating four discrete oscillators and reducing board area by >60%.	Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in modular switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing integer-related frequencies from a single 25 MHz crystal reference. Use Value: Enables single-crystal timing architecture with <100 ps output-to-output skew and deterministic phase relationships across data rates.
FPGA/ASIC Clock Tree	Broadcast Video Synchronization
Use Scenario: Supplying multiple domain-specific clocks (e.g., 200 MHz logic, 400 MHz DDR, 125 MHz SerDes) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Programmable clock source with independent voltage and format per output to match FPGA I/O standards (LVDS, HCSL, SSTL). Use Value: Eliminates need for external level translators and reduces power vs. discrete buffer solutions (typ. 45 mA core vs. >100 mA for four buffers).	Use Scenario: Distributing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks across video processing modules in broadcast encoders. IC Role / Device Role / Timing Role: Low-phase-noise clock generator supporting jitter cleaning and frequency translation from GPSDO or atomic reference. Use Value: Achieves <0.7 ps RMS jitter-well below SMPTE ST 2059-2 Class A limit (20 ps pk-pk)-without external jitter cleaners.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent enable/disable and SSC control per lane group.

Use Value: Meets PCIe Gen 4 common clock jitter requirement (≤0.45 ps RMS) while eliminating four discrete oscillators and reducing board area by >60%.

Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs in modular switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing integer-related frequencies from a single 25 MHz crystal reference.

Use Value: Enables single-crystal timing architecture with <100 ps output-to-output skew and deterministic phase relationships across data rates.

FPGA/ASIC Clock Tree

Broadcast Video Synchronization

Use Scenario: Supplying multiple domain-specific clocks (e.g., 200 MHz logic, 400 MHz DDR, 125 MHz SerDes) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Programmable clock source with independent voltage and format per output to match FPGA I/O standards (LVDS, HCSL, SSTL).

Use Value: Eliminates need for external level translators and reduces power vs. discrete buffer solutions (typ. 45 mA core vs. >100 mA for four buffers).

Use Scenario: Distributing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks across video processing modules in broadcast encoders.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator supporting jitter cleaning and frequency translation from GPSDO or atomic reference.

Use Value: Achieves <0.7 ps RMS jitter-well below SMPTE ST 2059-2 Class A limit (20 ps pk-pk)-without external jitter cleaners.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05575-GM	Higher integration: includes integrated LDOs, enhanced PCIe Gen 5 jitter (0.1 ps RMS), 32-QFN (5 × 5 mm)	Requires PCB redesign due to larger footprint and different pinout; supports higher-frequency outputs (up to 1.2 GHz)	Select when upgrading to PCIe Gen 5 or requiring integrated power regulation; not drop-in compatible.
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; 32-TQFP package	Lacks I²C programmability, frequency flexibility, and spread-spectrum capability; limited to pre-defined output frequencies	Select only for cost-sensitive, static-clock applications where field reconfiguration is unnecessary.

Compared with Si5332A-D05575-GM and ICS8430I-01T, the SI5338C-B05575-GMR uniquely balances field programmability, PCIe Gen 4 compliance, compact 4 × 4 mm QFN packaging, and proven industrial temperature operation-making it optimal for mid-generation upgrades and space-constrained designs where flexibility matters.

Availability

SI5338C-B05575-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10G/25G Ethernet switching infrastructure, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B05575-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in data center, telecom, and broadcast systems-emphasizing low jitter, flexible I²C configuration, and robust operation across extended temperature ranges.

FAQ

What is the maximum output frequency supported by SI5338C-B05575-GMR?

The SI5338C-B05575-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as defined in the synthesis architecture.

Does SI5338C-B05575-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B05575-GMR is validated for PCIe Gen 4 Common Clock mode with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz band), meeting the PCI-SIG Base Specification 4.0 rev 0.5 requirements when configured with appropriate PLL bandwidth (2–4 MHz) and CDR settings.

Can SI5338C-B05575-GMR operate with a 25 MHz crystal reference?

Yes, SI5338C-B05575-GMR accepts external crystals from 8 to 30 MHz. A 25 MHz crystal falls within the supported range and is commonly used for PCIe and Ethernet timing; load capacitance must be matched to the on-chip 12 pF setting per AN360 guidelines.

How is SI5338C-B05575-GMR programmed in-system?

SI5338C-B05575-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration is stored in one-time-programmable (OTP) memory, enabling field updates and persistent settings across power cycles.

What thermal management is required for SI5338C-B05575-GMR in continuous operation?

SI5338C-B05575-GMR has θ_JA = 37 °C/W (still air). For continuous 45 mA core current at +85 °C ambient, junction temperature remains below 150 °C if the exposed thermal pad is soldered to ≥2 cm² internal ground plane with ≥4 thermal vias. No heatsink is required under nominal conditions.

SI5338C-B05575-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05575-GMR FAQ

1.How can I place an order for SI5338C-B05575-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05575-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05575-GMR reliable?

The price and inventory of SI5338C-B05575-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05575-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05575-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05575-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05575-GMR?

SI5338C-B05575-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05575-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05575-GMR?

For technical support, including SI5338C-B05575-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05575-GMR requirements.

6.How does Aetrix verify that SI5338C-B05575-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05575-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05575-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05575-GMR?

All SI5338C-B05575-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05575-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05575-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05575-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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