Skyworks Solutions Inc. SI5338C-B05601-GM

Overview

SI5338C-B05601-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338C-B05601-GM datasheet, SI5338C-B05601-GM pinout, SI5338C-B05601-GM application, or SI5338C-B05601-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control (0.5–5.0% at 33–63 kHz), and phase/frequency increment/decrement resolution (20 ps / 1 ppm).

Technical Context

The SI5338C-B05601-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its patented MultiSynth enables true zero-ppm frequency accuracy on all four outputs without requiring external loop filters.

It supports six input types - differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and crystal (8–30 MHz) - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and independent output enable (OEB) and interrupt (INTR) pins for system-level timing supervision.

Key Specifications

Pinout & Package

SI5338C-B05601-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338C-B05602-GM, the SI5338C-B05601-GM offers identical electrical performance but requires full I²C configuration at power-up; versus Si5332A-D05601-GM, it provides proven industrial reliability and broader legacy support at the cost of higher jitter and no integrated crystal.

Availability

SI5338C-B05601-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clock distribution, and broadcast video/audio synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B05601-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing innovation.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems including networking, data center, and broadcast equipment where deterministic timing and multi-format flexibility are critical.

FAQ

What is the maximum output frequency supported by SI5338C-B05601-GM?

The SI5338C-B05601-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints.

Does SI5338C-B05601-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B05601-GM meets PCIe Gen 4 Common Clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL 100 MHz outputs and appropriate PLL bandwidth settings (2–4 MHz or 2–5 MHz).

Can SI5338C-B05601-GM operate with a single-ended input clock?

Yes, SI5338C-B05601-GM accepts single-ended CMOS, SSTL, or HSTL inputs on pins IN3 and IN4 across 5–350 MHz. Input thresholds are referenced to VDD (VIH = 0.7×VDD, VIL = 0.3×VDD), and slew rate should exceed 1 V/ns for optimal jitter performance.

How is phase alignment controlled across the four outputs of SI5338C-B05601-GM?

SI5338C-B05601-GM provides independent programmable initial phase offset (±45 ns range) and fine-grained phase increment/decrement (20 ps steps) per output. Skew between outputs is typically <100 ps when driven from the same MultiSynth stage and using identical output formats.

Is external programming required for SI5338C-B05601-GM to function?

Yes, SI5338C-B05601-GM is blank OTP and requires I²C configuration at power-up unless pre-programmed. Skyworks ClockBuilder Pro software generates configuration files and supports EEPROM programming; default state after POR is undefined until registers are written.