Skyworks Solutions Inc. SI5338C-B05602-GM
- Part No.:
- SI5338C-B05602-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05602-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,461
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338C-B05602-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338C-B05602-GM datasheet, SI5338C-B05602-GM pinout, SI5338C-B05602-GM application, or SI5338C-B05602-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).
Technical Context
The SI5338C-B05602-GM implements a two-stage PLL architecture: a high-stability reference stage (input frequency range 5–710 MHz) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Each synthesizer supports integer or fractional mode with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).
It features dual input paths - differential (IN1/IN2, IN5/IN6), single-ended CMOS (IN3/IN4), or external crystal (8–30 MHz) - and supports zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms, plus I²C/SMBus-compatible configuration, enable robust system-level timing control in FPGA, processor, and switch/router platforms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per channel; supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range |
| Spread Spectrum | Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate |
| Phase Adjustment | Independent per output, <20 ps step resolution, ±45 ns total range |
Pinout & Package
SI5338C-B05602-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.6 datasheet, page 33 (Pin Descriptions) and page 37 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended CMOS inputs | Support 5–200 MHz DC-coupled signals; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs | Four independent output drivers; each pair supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V per output bank; enables mixed-voltage clock distribution |
| VDD | Core supply | 1.8/2.5/3.3 V ± tolerance; powers PLL, MultiSynth, and control logic |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial bus (up to 400 kHz); used for register configuration and status readback |
| INTR | Interrupt output | Open-drain alarm signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables independent, any-frequency generation (0.16–710 MHz) on all four outputs with true zero ppm accuracy |
| PCIe Gen 4 compliance | Meets PCIe Base Spec 4.0 common clock jitter requirement (≤0.45 ps RMS) without external filtering |
| Independent output voltage control | Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs and ASICs |
| Glitchless frequency tuning | 1 ppm-step increment/decrement via dedicated pins or I²C, with update time as low as 667 ns |
| Programmable spread spectrum | On any output: selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only) |
| Zero-delay mode support | External feedback path allows synchronous clock forwarding with minimal propagation delay (2.5–4 ns) |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched skew (<100 ps) and PCIe Gen 4 SRNS compliance. Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane timing alignment required for Gen 4 link training and error-free 16 GT/s operation. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors on a telecom line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing three distinct Ethernet-standard frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board space vs. multiple fixed-frequency oscillators; supports flexible port density scaling without hardware change. |
| Broadcast Video Sync | FPGA-Based Video Processing |
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transmitters and video encoders in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-phase-jitter (0.7 ps RMS) clock generator supporting SMPTE ST 2082-1 and ST 2081-1 timing requirements. Use Value: Enables frame-accurate synchronization across multi-channel video pipelines; eliminates visible artifacts caused by sub-picosecond jitter-induced timing drift. |
Use Scenario: Supplying 300 MHz LVDS and 100 MHz CMOS clocks to Xilinx Versal and Intel Agilex FPGAs in real-time video analytics systems. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage per output (1.8 V LVDS, 3.3 V CMOS) and programmable phase offset (±45 ns). Use Value: Simplifies FPGA I/O bank power domain management; enables precise setup/hold timing margin optimization across heterogeneous logic blocks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05602-GM | Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 12 outputs via fanout | Targeted at ultra-low-jitter applications (e.g., 400G optical modules); requires no external crystal | Select when crystal integration, sub-0.4 ps jitter, or >4 outputs are required; higher cost and larger footprint (5 × 5 mm) |
| ICS853S01AGI-01LFT | Fixed-frequency, non-programmable quad LVDS buffer; 0.9 ps RMS jitter; no I²C interface or MultiSynth | Limited to pre-defined frequencies (e.g., 100/125/156.25 MHz); no spread spectrum or phase adjustment | Select for cost-sensitive, static-clocking designs where frequency flexibility and advanced features are unnecessary |
Compared with Si5332A-D05602-GM, SI5338C-B05602-GM offers lower system cost and smaller footprint but lacks integrated crystal and sub-0.4 ps jitter. Compared with ICS853S01AGI-01LFT, it provides full frequency programmability and PCIe Gen 4 compliance at the expense of higher complexity and bill-of-materials count.
Availability
SI5338C-B05602-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line cards, and broadcast video sync applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338C-B05602-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, with emphasis on design flexibility and system-level timing integrity.
FAQ
What is the maximum output frequency supported by SI5338C-B05602-GM in LVPECL format?
The SI5338C-B05602-GM supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This applies when using the MultiSynth™ synthesizer in integer mode with appropriate VCO settings. Frequencies above 350 MHz require careful layout and termination to maintain jitter performance below 1 ps RMS.
Does SI5338C-B05602-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338C-B05602-GM is compliant with PCIe Gen 4 SRNS requirements, achieving ≤0.32 ps RMS jitter under specified test conditions (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This is verified in Table 12 of the Skyworks Rev. 1.6 datasheet and confirmed using the Skyworks PCIe Clock Jitter Tool.
Can SI5338C-B05602-GM generate four different output frequencies simultaneously?
Yes, SI5338C-B05602-GM uses four independent MultiSynth™ engines to synthesize four distinct frequencies simultaneously - for example, 100 MHz (PCIe), 125 MHz (GbE), 156.25 MHz (10GbE), and 297 MHz (SDI) - all from a single 25 MHz crystal reference, with 0 ppm frequency error and <20 ps phase step resolution.
What is the function of the INTR pin on SI5338C-B05602-GM?
The INTR pin on SI5338C-B05602-GM is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) events. It connects directly to a microcontroller GPIO or FPGA interrupt controller, enabling real-time fault detection and system-level timing health monitoring without polling the I²C interface.
Is SI5338C-B05602-GM compatible with ClockBuilder Pro software?
Yes, SI5338C-B05602-GM is fully supported by Skyworks ClockBuilder Pro software (v3.x+), which provides GUI-based configuration, real-time jitter estimation, register map generation, and .hex file export for one-time programming of the device's OTP NVM. Configuration files generated for SI5338C-B05602-GM are not interchangeable with other Si5338 variants without validation.
SI5338C-B05602-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05602-GM FAQ
1.How can I place an order for SI5338C-B05602-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05602-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05602-GM reliable?
The price and inventory of SI5338C-B05602-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05602-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B05602-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05602-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05602-GM?
SI5338C-B05602-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05602-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05602-GM?
For technical support, including SI5338C-B05602-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05602-GM requirements.
6.How does Aetrix verify that SI5338C-B05602-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05602-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05602-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B05602-GM?
All SI5338C-B05602-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05602-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05602-GM part is unused and in its original packaging.
Return procedure for SI5338C-B05602-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338C-B05602-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

