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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05602-GMR

Name: SI5338C-B05602-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05602-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05602-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05602-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05602-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05602-GMR datasheet, SI5338C-B05602-GMR pinout, SI5338C-B05602-GMR application, or SI5338C-B05602-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338C-B05602-GMR implements a two-stage PLL architecture: a high-stability reference stage (VCO + N-divider) followed by four independent MultiSynth™ fractional-N synthesis stages (M0–M3), each feeding a configurable output driver. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage selection (1.5–3.3 V), programmable phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and configurable spread spectrum (33–63 kHz modulation rate, 0.5–5.0% spread). The device operates across –40 to +85 °C with 45 mA typical core current.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Count & Type	Four independent outputs: supports up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL) clocks simultaneously.
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution enables exact frequency matching for multi-protocol systems.
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); supports zero-delay mode via external feedback.
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver - enables mixed-voltage system clocking without level shifters.
Compliance	PCIe Gen 1/2/3/4 Common Clock; PCIe Gen 3 SRNS; JEDEC JESD78 latch-up compliant; HBM ESD rated at 2.5 kV.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3 (MSL3).

Pinout & Package

The SI5338C-B05602-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential reference; internal 100 Ω termination enabled by default.
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level inputs; VIH = 0.7×VDD, VIL = 0.3×VDD; 4 pF input capacitance.
IN5, IN6	Differential input pair 2	Second 5–710 MHz differential reference path; enables dual-reference redundancy or frequency translation.
CLK0A–CLK3B	Differential output pairs	Four fully independent outputs; each pair supports LVPECL/LVDS/HCSL/CML with selectable VDDOx (1.5–3.3 V).
VDDO0–VDDO3	Output buffer supplies	Independent power pins per output bank; decoupling required per VDDO to minimize crosstalk and jitter.
VDD	Core supply	1.8/2.5/3.3 V ±10% core rail; 45 mA typical current draw at 100 MHz on all outputs with 25 MHz refclk.
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz I²C bus; supports ClockBuilder Pro programming and real-time configuration updates.
INTR	Interrupt output	Open-drain status indicator; asserts low on loss-of-lock, loss-of-signal, or register-access error.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs - eliminates need for multiple crystals in multi-clock domain systems.
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps with <667 ns update time - enables dynamic clock scaling without output interruption.
Programmable phase alignment	±45 ns phase offset per output with <20 ps step resolution - supports precise skew management for SerDes lane deskew and DDR timing closure.
Configurable spread spectrum	Per-output SSC with 0.5–5.0% spread, 33–63 kHz modulation rate, and selectable center/down-spread - reduces EMI peak emissions in dense PCB layouts.
Loss detection alarms	Dedicated INTR pin reports loss-of-lock (5–10 ms detect time) and loss-of-signal (2.6–5 µs detect time) - enables system-level fault monitoring without host polling.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in data center top-of-rack switches. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) PCIe-compliant clocks with SRNS support and spread-spectrum capability. Use Value: Meets PCIe Gen 4 common clock jitter specification while enabling single-device replacement of four discrete oscillators - reducing BOM count and layout area by >60%.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in carrier-grade Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting simultaneous CMOS and LVDS outputs with independent voltage rails (1.8 V/2.5 V/3.3 V). Use Value: Eliminates need for separate oscillators and level translators; programmable phase offset aligns transmit/receive clock edges to meet IEEE 802.3ap skew limits.
Broadcast Video Sync	FPGA/ASIC Clock Distribution
Use Scenario: Delivering frame-synchronized 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transmitters, video processors, and genlock circuits in broadcast production equipment. IC Role / Device Role / Timing Role: High-precision quad clock generator with <10 ps pk-pk period jitter and programmable initial phase offset. Use Value: Enables sub-pixel timing alignment across multiple video paths; spread-spectrum control suppresses EMI in RF-sensitive studio environments.	Use Scenario: Supplying multiple clock domains (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver) to Xilinx Versal or Intel Agilex FPGAs in radar and test instrumentation. IC Role / Device Role / Timing Role: Configurable clock source supporting LVDS, HCSL, and CMOS outputs with independent VDDO per bank and glitchless frequency switching. Use Value: Reduces FPGA pin count and external buffering; phase adjustment ensures setup/hold margin compliance across heterogeneous clock trees.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in data center top-of-rack switches.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) PCIe-compliant clocks with SRNS support and spread-spectrum capability.

Use Value: Meets PCIe Gen 4 common clock jitter specification while enabling single-device replacement of four discrete oscillators - reducing BOM count and layout area by >60%.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in carrier-grade Ethernet switches.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting simultaneous CMOS and LVDS outputs with independent voltage rails (1.8 V/2.5 V/3.3 V).

Use Value: Eliminates need for separate oscillators and level translators; programmable phase offset aligns transmit/receive clock edges to meet IEEE 802.3ap skew limits.

Broadcast Video Sync

FPGA/ASIC Clock Distribution

Use Scenario: Delivering frame-synchronized 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transmitters, video processors, and genlock circuits in broadcast production equipment.

IC Role / Device Role / Timing Role: High-precision quad clock generator with <10 ps pk-pk period jitter and programmable initial phase offset.

Use Value: Enables sub-pixel timing alignment across multiple video paths; spread-spectrum control suppresses EMI in RF-sensitive studio environments.

Use Scenario: Supplying multiple clock domains (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver) to Xilinx Versal or Intel Agilex FPGAs in radar and test instrumentation.

IC Role / Device Role / Timing Role: Configurable clock source supporting LVDS, HCSL, and CMOS outputs with independent VDDO per bank and glitchless frequency switching.

Use Value: Reduces FPGA pin count and external buffering; phase adjustment ensures setup/hold margin compliance across heterogeneous clock trees.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05602-GM	Higher integration: integrated crystal option, lower jitter (0.35 ps RMS), 12-output capability, but larger 5 × 5 mm 32-QFN package.	Targets ultra-low-jitter applications (e.g., 400G optical modules) where board space permits larger footprint and cost premium is acceptable.	Select when PCIe Gen 5 or OTU4 jitter specs apply; avoid if 4 × 4 mm footprint or I²C-only programming is mandatory.
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock generator; no I²C programmability, no spread spectrum, no phase adjustment, 1.2 ps RMS jitter.	Suitable only for static, single-frequency designs (e.g., legacy PCIe Gen 2 systems) where reconfiguration is unnecessary.	Choose only for cost-sensitive, non-reprogrammable deployments; not viable for multi-protocol or field-upgradable systems.

Compared with Si5332A-D05602-GM and ICS853S01AGI-01LFT, the SI5338C-B05602-GMR delivers optimal balance of programmability, jitter performance, and compact 4 × 4 mm packaging - making it the preferred choice for PCIe Gen 4, 10GbE, and broadcast video systems requiring field-configurable timing.

Availability

SI5338C-B05602-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE switch clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05602-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed for high-performance, multi-protocol timing in data center, telecom, and broadcast systems - delivering programmable any-frequency synthesis with industry-leading jitter performance in minimal footprint.

FAQ

What is the maximum output frequency supported by the SI5338C-B05602-GMR on LVPECL outputs?

The SI5338C-B05602-GMR supports LVPECL outputs up to 710 MHz. This maximum applies when operating in integer synthesis mode with appropriate VCO and divider settings. Frequencies above 350 MHz are limited to two unique outputs simultaneously (Fvco/4 and Fvco/6), as specified in the functional description section of the datasheet.

Does the SI5338C-B05602-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, the SI5338C-B05602-GMR is explicitly stated as PCIe Gen 3 SRNS compliant and meets PCIe Gen 4 common clock jitter requirements (0.15–0.45 ps RMS). Its PLL loop bandwidth (1.6 MHz typical) and low deterministic jitter (<10 ps pk-pk) enable SRNS operation when configured with a 2–5 MHz PLL bandwidth and 10 MHz CDR bandwidth per PCIe Base Spec 4.0.

Can the SI5338C-B05602-GMR generate four different output frequencies simultaneously?

Yes, the SI5338C-B05602-GMR uses four independent MultiSynth™ engines to synthesize four distinct output frequencies simultaneously - each with 0 ppm precision and full format/voltage/format configurability. Output frequencies may range from 0.16 MHz to 710 MHz depending on selected format and synthesis mode.

What is the purpose of the RSVD_GND pin on the SI5338C-B05602-GMR?

The RSVD_GND pin (Pin 21) is a reserved ground terminal designated for mechanical stability and thermal dissipation. It must be connected to the PCB ground plane and is not internally connected to other ground nets. This pin improves thermal resistance (θJC = 10 °C/W) and provides additional grounding for the exposed thermal pad beneath the 24-QFN package.

How does the SI5338C-B05602-GMR handle loss-of-signal detection on its input clocks?

The SI5338C-B05602-GMR detects loss-of-signal (LOS) on differential inputs (IN1/IN2, IN5/IN6) within 2.6–5 µs and releases the alarm within 0.01–1 µs. Detection is disabled in PLL bypass mode below 5 MHz but remains functional down to 1 MHz in buffer mode. LOS status is reported via the open-drain INTR pin and corresponding status registers.

SI5338C-B05602-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05602-GMR FAQ

1.How can I place an order for SI5338C-B05602-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05602-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05602-GMR reliable?

The price and inventory of SI5338C-B05602-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05602-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05602-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05602-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05602-GMR?

SI5338C-B05602-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05602-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05602-GMR?

For technical support, including SI5338C-B05602-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05602-GMR requirements.

6.How does Aetrix verify that SI5338C-B05602-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05602-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05602-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05602-GMR?

All SI5338C-B05602-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05602-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05602-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05602-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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