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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05611-GM

Name: SI5338C-B05611-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05611-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05611-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05611-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05611-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common-clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4×4 mm 24-QFN package for FPGA and processor clocking applications.

For engineers reviewing the SI5338C-B05611-GM datasheet, SI5338C-B05611-GM pinout, SI5338C-B05611-GM application, or SI5338C-B05611-GM equivalent, key selection criteria include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, <20 ps phase step resolution, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential inputs (5–710 MHz).

Technical Context

The SI5338C-B05611-GM integrates a high-stability PLL with two-stage MultiSynth™ synthesis: first-stage PLL locks to input reference (crystal or clock), second-stage fractional-N MultiSynth™ synthesizers generate each of four outputs independently. Each output driver supports format and voltage configuration, enabling mixed-signal timing in multi-protocol systems.

It features loss-of-lock and loss-of-signal alarms, I²C/SMBus interface with ClockBuilder Pro software support, and configurable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation). External feedback mode enables zero-delay operation, and independent phase/frequency adjustment allows real-time dynamic tuning without glitches.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL to 250 MHz, CMOS to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range
Power Consumption	45 mA typ core current at 100 MHz on all outputs and 25 MHz refclk
Frequency Resolution	1 ppb synthesis resolution; true zero ppm accuracy on all outputs via integer/fractional MultiSynth™

Pinout & Package

SI5338C-B05611-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B to CLK3A, CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each configurable for format and voltage
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank; decoupling required per pin
VDD	Core supply	Single 1.8/2.5/3.3 V supply for PLL, logic, and MultiSynth™ engines
SCL, SDA	I²C interface	Standard SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock or loss-of-signal events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
Independent per-output format & voltage	Each of four outputs supports LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL with dedicated VDDO rail (1.5–3.3 V)
Glitchless frequency tuning	1 ppm step size with 667 ns update time via PINC/FDEC pins; no output interruption during adjustment
Programmable phase offset	±45 ns range with <20 ps step resolution; enables precise inter-channel skew control for SerDes alignment
Configurable spread spectrum	0.5–5.0% down-spread, 33–63 kHz modulation rate on any output; reduces EMI in dense PCB layouts
External feedback mode	Enables zero-delay clock distribution by feeding CLKOUT back as reference; eliminates PLL latency

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: High-speed switch ASIC requiring four synchronized clocks: 100 MHz PCIe RefClk, 156.25 MHz Ethernet, 250 MHz CPU interface, and 312.5 MHz SerDes lane clock. IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter, protocol-compliant clocks with PCIe Gen 4 SRNS and IEEE 802.3bj jitter compliance. Use Value: Eliminates four discrete oscillators; achieves 0.11–0.45 ps RMS jitter per PCIe Gen 4 spec using same silicon platform.	Use Scenario: 10GbE/25GbE line card needing 156.25 MHz, 312.5 MHz, and 625 MHz clocks for PHY, MAC, and packet processor, plus 100 MHz management clock. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering exact frequencies with integer-mode MultiSynth™ to avoid fractional spurs in high-speed links. Use Value: Enables single-chip timing for multi-rate Ethernet; supports both NRZ and PAM4 signaling via configurable output formats.
FPGA-Based Video Processing	Broadcast Audio/Video Sync
Use Scenario: Broadcast-grade video encoder FPGA requiring 27 MHz pixel clock, 74.25 MHz HDMI, 148.5 MHz dual-link, and 100 MHz system clock-all with sub-20 ps inter-channel skew. IC Role / Device Role / Timing Role: Precision clock generator with programmable phase offset and <100 ps output-to-output skew for pixel-accurate timing alignment. Use Value: Replaces multiple crystal oscillators and fanout buffers; maintains SMPTE ST 2082-1 timing integrity across all outputs.	Use Scenario: AES67/Ravenna audio-over-IP gateway needing 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz word clocks derived from a single 24.576 MHz master reference. IC Role / Device Role / Timing Role: High-resolution frequency translator generating exact audio sample rates with 1 ppb resolution and <0.7 ps RMS jitter. Use Value: Ensures bit-perfect audio synchronization across networked devices; avoids resampling artifacts in professional broadcast workflows.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: High-speed switch ASIC requiring four synchronized clocks: 100 MHz PCIe RefClk, 156.25 MHz Ethernet, 250 MHz CPU interface, and 312.5 MHz SerDes lane clock.

IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter, protocol-compliant clocks with PCIe Gen 4 SRNS and IEEE 802.3bj jitter compliance.

Use Value: Eliminates four discrete oscillators; achieves 0.11–0.45 ps RMS jitter per PCIe Gen 4 spec using same silicon platform.

Use Scenario: 10GbE/25GbE line card needing 156.25 MHz, 312.5 MHz, and 625 MHz clocks for PHY, MAC, and packet processor, plus 100 MHz management clock.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering exact frequencies with integer-mode MultiSynth™ to avoid fractional spurs in high-speed links.

Use Value: Enables single-chip timing for multi-rate Ethernet; supports both NRZ and PAM4 signaling via configurable output formats.

FPGA-Based Video Processing

Broadcast Audio/Video Sync

Use Scenario: Broadcast-grade video encoder FPGA requiring 27 MHz pixel clock, 74.25 MHz HDMI, 148.5 MHz dual-link, and 100 MHz system clock-all with sub-20 ps inter-channel skew.

IC Role / Device Role / Timing Role: Precision clock generator with programmable phase offset and <100 ps output-to-output skew for pixel-accurate timing alignment.

Use Value: Replaces multiple crystal oscillators and fanout buffers; maintains SMPTE ST 2082-1 timing integrity across all outputs.

Use Scenario: AES67/Ravenna audio-over-IP gateway needing 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz word clocks derived from a single 24.576 MHz master reference.

IC Role / Device Role / Timing Role: High-resolution frequency translator generating exact audio sample rates with 1 ppb resolution and <0.7 ps RMS jitter.

Use Value: Ensures bit-perfect audio synchronization across networked devices; avoids resampling artifacts in professional broadcast workflows.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and architecture; factory-programmed with fixed configuration (non-I²C reprogrammable)	Limited to pre-defined frequency sets; no runtime reconfiguration or dynamic tuning capability	Select when production volume justifies OTP programming and field updates are unnecessary
LMK04832ISQE/NOPB	Two PLLs, eight outputs, JESD204B support; higher power (85 mA), larger 48-QFN package	Targeted at RF/data converter timing; includes jitter cleaner mode and dual-loop architecture	Select when ultra-low additive jitter (<0.15 ps RMS) or JESD204B deterministic latency is required

Compared with Si5338A-B-GM, SI5338C-B05611-GM offers full I²C reprogrammability and dynamic frequency/phase tuning; compared with LMK04832ISQE/NOPB, it provides smaller footprint and lower power at the expense of JESD204B support and dual-loop cleaning.

Availability

SI5338C-B05611-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10/25GbE networking equipment, and FPGA-based broadcast video processing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05611-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for multi-protocol digital systems-designed to replace multiple discrete oscillators while supporting PCIe, Ethernet, Fibre Channel, and broadcast timing standards.

FAQ

What is the maximum output frequency supported by SI5338C-B05611-GM in LVPECL format?

The SI5338C-B05611-GM supports LVPECL outputs up to 710 MHz. This capability is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper layout for signal integrity and jitter performance.

Does SI5338C-B05611-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338C-B05611-GM is explicitly stated as PCIe Gen 3 SRNS compliant and meets PCIe Gen 4 common-clock jitter requirements (0.15–0.45 ps RMS). Its PLL bandwidth (1.6 MHz typ) and low phase jitter (0.7 ps RMS) satisfy the Gen 4 SRNS mask when configured per Skyworks AN562 and PCIe Base Spec 4.0 rev. 0.5.

Can SI5338C-B05611-GM generate four different output frequencies simultaneously?

Yes, SI5338C-B05611-GM uses four independent MultiSynth™ engines to synthesize four distinct frequencies simultaneously-each with 0 ppm precision and 1 ppb resolution. The device supports any combination within its frequency ranges (e.g., 100 MHz, 156.25 MHz, 312.5 MHz, and 625 MHz), subject to VCO and divider constraints per the synthesis stage architecture.

What input reference options does SI5338C-B05611-GM support?

SI5338C-B05611-GM accepts multiple reference sources: external crystal (8–30 MHz), single-ended CMOS clock (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clock (5–710 MHz). Input flexibility enables use with legacy crystals, recovered clocks, or high-speed serial references-verified in Tables 6 and 8–11 of the datasheet.

Is ClockBuilder Pro software required to configure SI5338C-B05611-GM?

No, ClockBuilder Pro is optional but strongly recommended for SI5338C-B05611-GM configuration. The device supports standard I²C/SMBus writes to internal registers, but ClockBuilder Pro automates register calculation, validates MultiSynth™ settings, generates configuration files, and verifies PCIe/Ethernet compliance-reducing development time and avoiding synthesis errors.

SI5338C-B05611-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05611-GM FAQ

1.How can I place an order for SI5338C-B05611-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05611-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05611-GM reliable?

The price and inventory of SI5338C-B05611-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05611-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05611-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05611-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05611-GM?

SI5338C-B05611-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05611-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05611-GM?

For technical support, including SI5338C-B05611-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05611-GM requirements.

6.How does Aetrix verify that SI5338C-B05611-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05611-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05611-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05611-GM?

All SI5338C-B05611-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05611-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05611-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05611-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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