Skyworks Solutions Inc. SI5338C-B05617-GM

Overview

SI5338C-B05617-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338C-B05617-GM datasheet, SI5338C-B05617-GM pinout, SI5338C-B05617-GM application, or SI5338C-B05617-GM equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), PCIe Gen 4 common clock compliance, independent per-output voltage control (1.5/1.8/2.5/3.3 V), 4×4 mm 24-QFN package, and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338C-B05617-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers. Each output path includes configurable divider chains (R/M/N/P), programmable phase offset (<20 ps step), and glitchless frequency increment/decrement (1 ppm steps).

It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and enables zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring for system reliability.

Key Specifications

Pinout & Package

SI5338C-B05617-GM is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is top-left (IN1), pin numbering proceeds counter-clockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D05617-GM and ICS853S01AGI-01LFT, the SI5338C-B05617-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and per-output voltage/format control - making it optimal for multi-standard, high-flexibility timing in networking and broadcast systems where post-silicon frequency changes are expected.

Availability

SI5338C-B05617-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25 GbE switch clocking, and broadcast video sync generation requiring stable component supply, full traceability, and lifecycle continuity.

Supply support for SI5338C-B05617-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure and mobile markets.

The Si5338 family was designed for high-performance, multi-protocol clock generation in data center switches, telecom line cards, and broadcast equipment - emphasizing low jitter, PCIe compliance, and software-configurable flexibility over fixed-function alternatives.

FAQ

What is the maximum output frequency supported by the SI5338C-B05617-GM?

The SI5338C-B05617-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated - specifically Fvco/4 and Fvco/6 - due to internal VCO constraints. All outputs maintain 0.7 ps RMS typical jitter within their respective rated ranges.

Does the SI5338C-B05617-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B05617-GM meets PCIe Gen 4 Common Clock specifications with 0.15–0.45 ps RMS jitter (12 kHz–20 MHz) when configured per Skyworks AN562 guidelines. It achieves this using a 2–5 MHz PLL bandwidth and CDR = 10 MHz, validated with the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can the SI5338C-B05617-GM generate different output voltages simultaneously?

Yes, the SI5338C-B05617-GM provides four independent VDDOx supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (1.5 V) outputs without external level shifters - a key enabler for mixed-voltage FPGA and ASIC interfaces.

How is the SI5338C-B05617-GM programmed and configured?

The SI5338C-B05617-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. This GUI tool enables full register configuration, jitter optimization, PCIe compliance validation, and one-click .hex file generation for OTP programming. Configuration persists in on-chip NVM (OTP), eliminating boot-time host intervention.

What input reference options does the SI5338C-B05617-GM support?

The SI5338C-B05617-GM accepts multiple reference sources: 8–30 MHz crystal (differential), 5–200 MHz CMOS (single-ended), 5–350 MHz SSTL/HSTL (single-ended), or 5–710 MHz differential (AC-coupled). Input flexibility enables use in legacy systems with existing clocks or new designs with optimized crystal selection per AN360 guidelines.